Tunnel field-effect transistors (TFET): modelling and simulation JK Mamidala, R Vishnoi, P Pandey John Wiley & Sons, 2016 | 149 | 2016 |
Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport R Vishnoi, MJ Kumar IEEE Transactions on Electron Devices 61 (6), 1936-1942, 2014 | 117 | 2014 |
Compact analytical drain current model of gate-all-around nanowire tunneling FET R Vishnoi, MJ Kumar IEEE Transactions on Electron Devices 61 (7), 2599-2603, 2014 | 99 | 2014 |
A pseudo-2-D-analytical model of dual material gate all-around nanowire tunneling FET R Vishnoi, MJ Kumar IEEE Transactions on Electron Devices 61 (7), 2264-2270, 2014 | 78 | 2014 |
A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling P Pandey, R Vishnoi, MJ Kumar Journal of Computational Electronics 14, 280-287, 2015 | 44 | 2015 |
An accurate compact analytical model for the drain current of a TFET from subthreshold to strong inversion R Vishnoi, MJ Kumar IEEE Transactions on Electron Devices 62 (2), 478-484, 2015 | 44 | 2015 |
2-D analytical model for the threshold voltage of a tunneling FET with localized charges R Vishnoi, MJ Kumar IEEE Transactions on Electron Devices 61 (9), 3054-3059, 2014 | 44 | 2014 |
A compact analytical model for the drain current of gate-all-around nanowire tunnel FET accurate from sub-threshold to ON-state R Vishnoi, MJ Kumar IEEE Transactions on Nanotechnology 14 (2), 358-362, 2015 | 36 | 2015 |
Drain current model for SOI TFET considering source and drain side tunneling P Pandey, R Vishnoi, MJ Kumar 2014 IEEE 2nd international conference on emerging electronics (ICEE), 1-5, 2014 | 10 | 2014 |
DC drain current model for tunnel FETs considering source and drain depletion regions R Vishnoi, P Panday, MJ Kumar 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 3 | 2017 |
Two dimensional analytical model for the threshold voltage of a Gate All Around Nanowire tunneling FET with localized charges R Vishnoi, MJ Kumar 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 769-773, 2015 | 1 | 2015 |
Modelling of nanoscale tunnelling field effect transistors R Vishnoi IIT Delhi, 2016 | | 2016 |
A Compact Analytical Model for the drain current of a TFET with non-abrupt doping profile incorporating the effect of band-gap narrowing R Vishnoi, MJ Kumar 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 920-923, 2015 | | 2015 |
A novel back gated GaN/AlGaN HEMT structure for biological sensing applications S Kejriwal, R Vishnoi, A Dhawan 2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-4, 2014 | | 2014 |
Numerical study of the Threshold Voltage of TFETs with localized charges R Vishnoi, MJ Kumar 2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-3, 2014 | | 2014 |
Alternative MOS transistor structures and substrate materials P Debashis, R Vishnoi, S Jain, S Bansal, S Jain | | |