| A 0.297-pJ/bit 50.4-Gb/s/wire inverter-based short-reach simultaneous bi-directional transceiver for die-to-die interface in 5-nm CMOS Y Nishi, JW Poulton, WJ Turner, X Chen, S Song, B Zimmer, SG Tell, ... IEEE Journal of Solid-State Circuits 58 (4), 1062-1073, 2023 | 22 | 2023 |
| An ASIC-Ready 1.25–6.25 Gb/s SerDes in 90nm CMOS with multi-standard compatibility Y Nishi, K Abe, J Ribo, B Roederer, A Gopalan, M Benmansour, A Ho, ... 2008 IEEE Asian Solid-State Circuits Conference, 37-40, 2008 | 18 | 2008 |
| Method and apparatus for receiving burst data without using external detection signal Y Nishi, M Konishi US Patent 8,649,473, 2014 | 15 | 2014 |
| Circuit and method for current-mode output driver with pre-emphasis Y Nishi US Patent 8,228,096, 2012 | 15 | 2012 |
| Circuit and method for current-mode output driver with pre-emphasis Y Nishi US Patent 8,659,325, 2014 | 10 | 2014 |
| Method and apparatus for receiving burst data without using external detection signal Y Nishi, M Konishi US Patent App. 12/496,159, 2011 | 9 | 2011 |
| Passive and active reduction techniques for on-chip high-frequency digital power supply noise E Bohannon, C Urban, M Pude, Y Nishi, A Gopalan, PR Mukund IEEE transactions on very large scale integration (VLSI) systems 18 (1), 157-161, 2009 | 9 | 2009 |
| An analytical propagation delay model with power supply noise effects M Pude, C Washburn, PR Mukund, K Abe, Y Nishi 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006 | 5 | 2006 |
| Low-voltage, high-accuracy current mirror circuit Y Nishi US Patent App. 13/764,464, 2014 | 4 | 2014 |
| Method and system for yield enhancement A Gopalan, Y Nishi US Patent App. 12/000,761, 2009 | 4 | 2009 |
| Reverse scaling for improved bandwidth in equalizers S Gondi, Y Nishi US Patent App. 11/214,910, 2006 | 4 | 2006 |
| Method and apparatus for receiving burst data without using external detection signal Y Nishi, M Konishi US Patent 8,995,595, 2015 | 3 | 2015 |
| A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS Y Nishi, JW Poulton, WJ Turner, X Chen, S Song, B Zimmer, SG Tell, ... IEEE Journal of Solid-State Circuits, 2023 | 1 | 2023 |
| Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling X Chen, Y Nishi, J Poulton US Patent App. 17/931,472, 2023 | | 2023 |
| Differential output buffer having mixing and output stages Y Nishi, PB Ramakrishna, SR Madala US Patent 9,118,321, 2015 | | 2015 |
| V. CONCLUSION AND FUTURE WORK E Bohannon, C Urban, M Pude, Y Nishi, A Gopalan, PR Mukund IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18 (1), 157, 2010 | | 2010 |
