| An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS S Vangal, J Howard, G Ruhl, S Dighe, H Wilson, J Tschanz, D Finan, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 949 | 2007 |
| An 80-tile sub-100-w teraflops processor in 65-nm cmos SR Vangal, J Howard, G Ruhl, S Dighe, H Wilson, J Tschanz, D Finan, ... IEEE Journal of solid-state circuits 43 (1), 29-41, 2008 | 909 | 2008 |
| A 5-GHz mesh interconnect for a teraflops processor Y Hoskote, S Vangal, A Singh, N Borkar, S Borkar IEEE micro 27 (5), 51-61, 2007 | 875 | 2007 |
| A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010 | 844 | 2010 |
| A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ... IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010 | 527 | 2010 |
| The 48-core SCC processor: the programmer's view TG Mattson, RF Van der Wijngaart, M Riepen, T Lehnig, P Brett, W Haas, ... SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 363 | 2010 |
| A 280mV-to-1.2 V wide-operating-range IA-32 processor in 32nm CMOS S Jain, S Khare, S Yada, V Ambili, P Salihundam, S Ramani, ... 2012 IEEE international solid-state circuits conference, 66-68, 2012 | 344 | 2012 |
| Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 275 | 2007 |
| Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core teraflops processor S Dighe, SR Vangal, P Aseron, S Kumar, T Jacob, KA Bowman, J Howard, ... IEEE Journal of Solid-State Circuits 46 (1), 184-193, 2010 | 175 | 2010 |
| A 2 Tb/s 64 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS P Salihundam, S Jain, T Jacob, S Kumar, V Erraguntla, Y Hoskote, ... IEEE journal of solid-state circuits 46 (4), 757-766, 2011 | 145 | 2011 |
| Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique S Narendra, J Tschanz, J Hofsheier, B Bloechel, S Vangal, Y Hoskote, ... 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 117 | 2004 |
| Selective node engineering for chip-level soft error rate improvement [in cmos] T Karnik, S Vangal, V Veeramachaneni, P Hazucha, V Erraguntla, ... 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 2002 | 101 | 2002 |
| 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS S Narendra, M Haycock, V Govindarajulu, V Erraguntla, H Wilson, ... 2002 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2002 | 101 | 2002 |
| A 6.2-GFlops floating-point multiply-accumulator with conditional normalization SR Vangal, YV Hoskote, NY Borkar, A Alvandpour IEEE journal of solid-state circuits 41 (10), 2314-2323, 2006 | 95 | 2006 |
| 5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/CMOS S Vangal, MA Anders, N Borkar, E Seligman, V Govindarajulu, ... IEEE Journal of Solid-State Circuits 37 (11), 1421-1432, 2002 | 88 | 2002 |
| Hardware-based multi-threading for packet processing Y Hoskote, SR Vangal, VK Erraguntla, NY Borkar US Patent 7,668,165, 2010 | 86 | 2010 |
| Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor S Dighe, S Vangal, P Aseron, S Kumar, T Jacob, K Bowman, J Howard, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 174-175, 2010 | 71 | 2010 |
| Network protocol engine SR Vangal, Y Hoskote, NY Borkar, J Xu, VK Erraguntla, SY Borkar US Patent 7,181,544, 2007 | 70 | 2007 |
| Performance and traffic aware heterogeneous interconnection network SR Vangal, NY Borkar, Z Fang US Patent 8,379,659, 2013 | 67 | 2013 |
| A TCP Offload Accelerator for 10 Gb/s Ethernet in 90-nm CMOS Y Hoskote, BA Bloechel, GE Dermer, V Erraguntla, D Finan, J Howard, ... IEEE Journal of Solid-State Circuits 38 (11), 1866-1875, 2003 | 66 | 2003 |
