| Two new low-power full adders based on majority-not gates K Navi, MH Moaiyeri, RF Mirzaee, O Hashemipour, BM Nezhad Microelectronics Journal 40 (1), 126-130, 2009 | 183 | 2009 |
| A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits MH Moaiyeri, RF Mirzaee, A Doostaregan, K Navi, O Hashemipour IET Computers & Digital Techniques 7 (4), 167-181, 2013 | 134 | 2013 |
| Efficient CNTFET-based ternary full adder cells for nanoelectronics MH Moaiyeri, RF Mirzaee, K Navi, O Hashemipour Nano-Micro Letters 3, 43-50, 2011 | 96 | 2011 |
| High-speed full adder based on minority function and bridge style for nanoscale K Navi, HH Sajedi, RF Mirzaee, MH Moaiyeri, A Jalali, O Kavehei Integration 44 (3), 155-162, 2011 | 85 | 2011 |
| Design and analysis of a high-performance CNFET-based Full Adder MH Moaiyeri, RF Mirzaee, K Navi, A Momeni International Journal of Electronics 99 (1), 113-130, 2012 | 74 | 2012 |
| Novel direct designs for 3-input XOR function for low-power and high-speed applications MH Moaiyeri, RF Mirzaee, K Navi, T Nikoubin, O Kavehei International Journal of Electronics 97 (6), 647-662, 2010 | 65 | 2010 |
| Towards effective offloading mechanisms in fog computing M Sheikh Sofla, M Haghi Kashani, E Mahdipour, R Faghih Mirzaee Multimedia Tools and Applications 81 (2), 1997-2042, 2022 | 63 | 2022 |
| Two New Low-Power and High-Performance Full Adders. MH Moaiyeri, RF Mirzaee, K Navi J. Comput. 4 (2), 119-126, 2009 | 59 | 2009 |
| High-efficient circuits for ternary addition RF Mirzaee, K Navi, N Bagherzadeh VLSI Design 2014, 10-10, 2014 | 50 | 2014 |
| High speed NP-CMOS and multi-output dynamic full adder cells RF Mirzaee, MH Moaiyeri, K Navi International Journal of Electrical and Electronics Engineering 4 (4), 2010 | 44 | 2010 |
| A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector YS Mehrabani, RF Mirzaee, Z Zareei, SM Daryabari Journal of Circuits, Systems and Computers 26 (05), 1750082, 2017 | 41 | 2017 |
| Dramatically low-transistor-count high-speed ternary adders RF Mirzaee, MH Moaiyeri, M Maleknejad, K Navi, O Hashemipour 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 170-175, 2013 | 36 | 2013 |
| Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic RF Mirzaee, T Nikoubin, K Navi, O Hashemipour Microelectronics Journal 44 (12), 1238-1250, 2013 | 35 | 2013 |
| A new robust and high-performance hybrid full adder cell RF Mirzaee, MH Moaiyeri, H Khorsand, K Navi Journal of Circuits, Systems, and Computers 20 (04), 641-655, 2011 | 32 | 2011 |
| Analytical review of noise margin in MVL: clarification of a deceptive matter M Takbiri, R Faghih Mirzaee, K Navi Circuits, Systems, and Signal Processing 38 (9), 4280-4301, 2019 | 29 | 2019 |
| Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 K Shahbazi, M Eshghi, RF Mirzaee Engineering Science and Technology, an International Journal 20 (4), 1308-1317, 2017 | 28 | 2017 |
| Ultra high speed full adders K Navi, RF Mirzaee, MH Moaiyeri, BM Nezhad, O Hashemipour, K Shams IEICE Electronics Express 5 (18), 744-749, 2008 | 27 | 2008 |
| Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4≤m≤10) compressors S Mehrabi, RF Mirzaee, S Zamanzadeh, K Navi, O Hashemipour International Journal of High Performance Systems Architecture 4 (4), 231-241, 2013 | 26 | 2013 |
| A novel 3D three/five-input majority-based full adder in nanomagnetic logic F Farzaneh, R Faghih Mirzaee, K Navi Journal of Computational Electronics 18, 364-373, 2019 | 16 | 2019 |
| CNFET-based design of energy-efficient symmetric three-input XOR and full adder circuits S Mehrabi, RF Mirzaee, MH Moaiyeri, K Navi, O Hashemipour Arabian Journal for Science and Engineering 38, 3367-3382, 2013 | 16 | 2013 |
