| Jutge. org: Characteristics and experiences J Petit, S Roura, J Carmona, J Cortadella, J Duch, O Gimnez, A Mani, ... IEEE Transactions on Learning Technologies 11 (3), 321-333, 2017 | 48 | 2017 |
| Mining structured Petri nets for the visualization of process behavior J de San Pedro, J Cortadella Proceedings of the 31st Annual ACM Symposium on Applied Computing, 839-846, 2016 | 29 | 2016 |
| Log-based simplification of process models J De San Pedro, J Carmona, J Cortadella Business Process Management: 13th International Conference, BPM 2015 …, 2015 | 25 | 2015 |
| Discovering duplicate tasks in transition systems for the simplification of process models J de San Pedro, J Cortadella Business Process Management: 14th International Conference, BPM 2016, Rio de …, 2016 | 20 | 2016 |
| Analytical performance modeling of hierarchical interconnect fabrics N Nikitin, J de_San Pedro, J Carmona, J Cortadella 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 107-114, 2012 | 14 | 2012 |
| Architectural exploration of large-scale hierarchical chip multiprocessors N Nikitin, J de San Pedro, J Cortadella IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 13 | 2013 |
| Integrating formal verification in an online judge for e-learning logic circuit design J de San Pedro, J Carmona, J Cortadella, J Petit Proceedings of the 43rd ACM technical symposium on Computer Science …, 2012 | 11 | 2012 |
| Physical-aware system-level design for tiled hierarchical chip multiprocessors J Cortadella, J de San Pedro, N Nikitin, J Petit Proceedings of the 2013 ACM International symposium on Physical Design, 3-10, 2013 | 4 | 2013 |
| Specification mining for asynchronous controllers J de San Pedro, T Bourgeat, J Cortadella 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems …, 2016 | 3 | 2016 |
| Physical planning for the architectural exploration of large-scale chip multiprocessors J de San Pedro, N Nikitin, J Cortadella, J Petit 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 1-2, 2013 | 3 | 2013 |
| A hierarchical approach for generating regular floorplans J de San Pedro, J Cortadella, A Roca 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 655-662, 2014 | 2 | 2014 |
| Structure discovery techniques for circuit design and process model visualization J San Pedro Martín Universitat Politècnica de Catalunya, 2017 | | 2017 |
| A Simulation framework for hierarchical Network-on-Chip systems J San Pedro Martín Universitat Politècnica de Catalunya, 2012 | | 2012 |
| An environment for the automatic verification of digital circuits J San Pedro Martín Universitat Politècnica de Catalunya, 2011 | | 2011 |
| NOCS 2013 Author Index H Amano, C Azar, E Azarkhish, L Benini, SJ Chen, YR Chen, S Chevobbe, ... | | |
