| Strategic reduction of area and power in FIR filter architecture for ECG signal acquisition S Janwadkar, R Dhavse 2020 IEEE 17th India Council International Conference (INDICON), 1-7, 2020 | 7 | 2020 |
| Qualitative and quantitative analysis of parallel-prefix adders S Janwadkar, R Dhavse Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019, 71-88, 2020 | 7 | 2020 |
| Design and performance evaluation of hybrid full adder for extensive PDP reduction S Janwadkar, S Das 2018 3rd International Conference for Convergence in Technology (I2CT), 1-6, 2018 | 7 | 2018 |
| Power and area efficient FIR filter architecture in digital encephalography systems S Janwadkar, R Dhavse E-Prime-Advances in Electrical Engineering, Electronics and Energy 4, 100148, 2023 | 5 | 2023 |
| Design and implementation of a GPS based personal tracking system S Janwadkar, D Bhavar, MT Kolte 2016 IEEE 1st International Conference on Power Electronics, Intelligent …, 2016 | 5 | 2016 |
| Investigation and analysis of power performance area (ppa) cards of digital multiplier architectures S Janwadkar, R Dhavse Journal of Circuits, Systems and Computers 31 (13), 2250239, 2022 | 3 | 2022 |
| Strategic design and optimization of Vedic low pass FIR filter for ECG signals S Janwadkar, R Dhavse Proceeding of Fifth International Conference on Microelectronics, Computing …, 2021 | 3 | 2021 |
| Design & implementation of high speed low power scan flip-flop S Janwadkar, MT Kolte 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 3 | 2016 |
| Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems: A Vedic Mathematics Approach S Janwadkar, R Dhavse 2020 IEEE REGION 10 CONFERENCE (TENCON), 153-158, 2020 | 1 | 2020 |
| Embedded logic flip-flops: a conceptual review S Janwadkar, MT Kolte International Journal of Engineering and Management Research (IJEMR) 6 (1 …, 2016 | 1 | 2016 |
| ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography S Janwadkar, R Dhavse Microprocessors and Microsystems, 105048, 2024 | | 2024 |
| ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier S Janwadkar, R Dhavse International Journal of Circuit Theory and Applications 52 (4), 1621-1646, 2024 | | 2024 |
| XOR-Free Approach Towards Realization of Low Pass FIR Filter in Bio-Medical Signal Acquisition: Vedic Multiplier-based ASIC Implementation S Janwadkar, R Dhavse 2023 IEEE 20th India Council International Conference (INDICON), 838-843, 2023 | | 2023 |
| Implementation of 4X4 Embedded Logic Memory for High Speed Applications S Janwadkar, MT Kolte iJARS International Journal of Engineering 2 (4), 2017 | | 2017 |
