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Suman Das
Suman Das
Assistant Professor, Sikkim Manipal Institute of Technology, Sikkim Manipal University
Verified email at smit.smu.edu.in
Title
Cited by
Cited by
Year
Detection and area calculation of brain tumour from MRI images using MATLAB
S Das, NN Siddiqui, N Kriti, SP Tamang
International Journal 4 (1), 35, 2017
152017
Dipterocarp forests of Bangladesh and their management.
S Das
Bano Biggyan Patrika 9 (1/2), 71-86, 1980
121980
Gate-on-drain overlapped L-shaped channel Tunnel FET as label-free biosensor
S Das, B Sharma
Silicon, 2021
92021
Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study
S Das, A Chattopadhyay, S Tewari
IEEE Transactions on Electron Devices 69 (11), 6430-6437, 2022
52022
A programme for the procurement of improved forest tree seeds in Bangladesh.
N Jones, S Das
51979
Asymmetric-elevated-source-drain TFET: A fairly scalable and reliable device architecture for sub-400-mV low-stand-by-power digital applications
S Das, A Chattopadhyay, S Tewari
IETE Technical Review 39 (2), 316-327, 2022
42022
Minimization of Drain-End Leakage of a U-Shaped Gated Tunnel FET for Low Standby Power (LSTP) Application
S Das, A Chattopadhyay, S Tewari
Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019 …, 2021
32021
Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness
S Das, S Tewari, A Chattopadhyay
AEU-International Journal of Electronics and Communications 168, 154714, 2023
12023
Architecture-and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective
S Das, A Chattopadhyay, S Tewari
Silicon 14 (16), 10719-10727, 2022
12022
nTunnel FET (nTFET) reliability study against positive bias temperature instability (PBTI) for different device architectures
S Das, A Chattopadhyay, S Tewari
Proceedings of the Fourth International Conference on Microelectronics …, 2021
12021
VLSI Implementation of Booth’s Multiplier Using Different Adders
U Sarkar, R Nath, S Das
Advances in Communication, Devices and Networking: Proceedings of ICCDN 2017 …, 2018
12018
FPGA based Security Login System using GSM with OTP Generation
S Subba, B Dahal, N Rai, R Banstola, S Das, SP Tamang
International Journal of Advanced Engineering Research and Science (IJAERS …, 2017
12017
An efficient modelling of amorphous silicon and polycrystalline silicon thin film transistor for AMOLED display using MATLAB
S Das, S Chatterjee
2016 International Conference on Inventive Computation Technologies (ICICT …, 2016
12016
Ab Initio Investigation of Optical and Electronic Properties of Pt‐Doped Pentagonal PdSe2 Monolayer
B Chettri, P Karki, P Chettri, SK Das, S Das, B Sharma
physica status solidi (b), 2300335, 2024
2024
Thermal Effect of Analog/RF Performance, Linearity and Harmonic Distortion for L-Gate TFET
S Das, B Sharma
Silicon 14 (15), 10071-10079, 2022
2022
A MATLAB-Based Simulator for Amorphous Silicon and Polycrystalline Silicon Thin Film Transistor
S Das, S Datta, S Chatterjee
Advances in Electronics, Communication and Computing: ETAEERE-2016, 733-744, 2018
2018
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