| Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs SK Swain, A Dutta, S Adak, SK Pati, CK Sarkar Microelectronics Reliability 61, 24-29, 2016 | 41 | 2016 |
| High performance AlInN/AlN/GaN p-GaN back barrier gate-recessed enhancement-mode HEMT S Adak, A Sarkar, S Swain, H Pardeshi, SK Pati, CK Sarkar Superlattices and Microstructures 75, 347-357, 2014 | 36 | 2014 |
| Nanotechnology: synthesis to applications S Roy, CK Ghosh, CK Sarkar CRC Press, 2017 | 34 | 2017 |
| Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs SK Swain, S Adak, SK Pati, CK Sarkar Superlattices and Microstructures 97, 258-267, 2016 | 24 | 2016 |
| Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage S Adak, SK Swain, A Singh, H Pardeshi, SK Pati, CK Sarkar Physica E: Low-dimensional Systems and Nanostructures 64, 152-157, 2014 | 19 | 2014 |
| Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DG-MOSFETs S Adak, SK Swain, A Dutta, H Rahaman, CK Sarkar Nano 11 (09), 1650101, 2016 | 15 | 2016 |
| Effect of channel thickness and doping concentration on sub-threshold performance of Graded Channel and gate stack DG MOSFETs SK Swain, S Adak, B Sharma, SK Pati, CK Sarkar Journal of Low Power Electronics 11 (3), 366-372, 2015 | 15 | 2015 |
| Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET SK Swain, SK Das, SM Biswal, S Adak, AAS Umakanta Nanda, D Navak, ... Devices for Integrated Circuit (DevIC), 2019 | 11 | 2019 |
| Impact of gate engineering in enhancement mode n++ GaN/InAlN/AlN/GaN HEMTs S Adak, SK Swain, H Rahaman, CK Sarkar Superlattices and Microstructures 100, 306-314, 2016 | 11 | 2016 |
| Study of linearity performance of graded channel gate stacks double gate MOSFET with respect to high-K oxide thickness SK Swain, SK Das, S Adak Silicon 12 (7), 1567-1574, 2020 | 10 | 2020 |
| Comparative assesment of ground plane and strained based FDSOI MOSFET A Singh, S Adak, H Pardeshi, A Sarkar, CK Sarkar Informacije MIDEM 45 (1), 73-79, 2015 | 10 | 2015 |
| Performance analysis of gate stack DG-MOSFET for biosensor applications SK Parija, SK Swain, SM Biswal, S Adak, P Dutta Silicon 14 (14), 8371-8379, 2022 | 7 | 2022 |
| Comparison study of dg-mosfet with and without gate stack configuration for biosensor applications SK Parija, SK Swain, S Adak, SM Biswal, P Dutta Silicon 14 (7), 3629-3640, 2022 | 7 | 2022 |
| Comparative study on analog & RF parameter of InALN/AlN/GaN normally off HEMTs with and without AlGAN back barrier N Chand, SK Swain, SM Biswal, A Sarkar, S Adak 2021 Devices for Integrated Circuit (DevIC), 616-620, 2021 | 6 | 2021 |
| Impact of high-K dielectric materials on performance analysis of underlap In0.17Al0.83N/GaN DG-MOSHEMTs S Adak Nano, 2019 | 5 | 2019 |
| Effect of doping in p-GaN gate on DC performances of AlGaN/GaN normally-off scaled HFETs S Adak, SK Swain, H Rahaman, CK Sarkar 2017 Devices for Integrated Circuit (DevIC), 372-375, 2017 | 5 | 2017 |
| Effect of AlN spacer layer thickness on device performance of AIInN/AlN/GaN MOSHEMT S Adak, SK Swain, H Pardeshi, H Rahman, CK Sarkar 2015 International Conference on Computing Communication Control and …, 2015 | 5 | 2015 |
| OFDMA-PON: High Speed PON Access System S Biswas, S Adak International Journal of Soft Computing 1, 2010 | 5 | 2010 |
| Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier N Chand, S Adak, SK Swain, SM Biswal, A Sarkar Computers & Electrical Engineering 98, 107695, 2022 | 4 | 2022 |
| Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs S Adak, N Chand, SK Swain, A Sarkar Devices for Integrated Circuit (DevIC), 2019 | 4 | 2019 |
Sudhansu Kumar PatiSilicon Institute of technology, Bhubaneswar, OdishaVerified email at silicon.ac.in
