| Analog/mixed-signal hardware error modeling for deep learning inference AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 71 | 2019 |
| Interference robust detector-first near-zero power wake-up receiver J Moody, P Bassirian, A Roy, N Liu, NS Barker, BH Calhoun, SM Bowers IEEE Journal of Solid-State Circuits 54 (8), 2149-2162, 2019 | 69 | 2019 |
| A− 76dBm 7.4 nW wakeup radio with automatic offset compensation J Moody, P Bassirian, A Roy, N Liu, S Pancrazio, NS Barker, BH Calhoun, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 452-454, 2018 | 62 | 2018 |
| A 2.5 ppm/° C 1.05-MHz relaxation oscillator with dynamic frequency-error compensation and fast start-up time N Liu, R Agarwala, A Dissanayake, DS Truesdell, S Kamineni, ... IEEE Journal of Solid-State Circuits 54 (7), 1952-1959, 2019 | 33 | 2019 |
| A battery-less 507nW SoC with integrated platform power manager and SiP interfaces F Yahya, CJ Lukas, J Breiholz, A Roy, HN Patel, NX Liu, X Chen, A Kosari, ... 2017 Symposium on VLSI Circuits, C338-C339, 2017 | 29 | 2017 |
| A-106dBm 33nW bit-level duty-cycled tuned RF wake-up receiver J Moody, A Dissanayake, H Bishop, R Lu, N Liu, D Duvvuri, A Gao, ... 2019 symposium on VLSI Circuits, C86-C87, 2019 | 26 | 2019 |
| A 1.02 μW battery-less, continuous sensing and post-processing SiP for wearable applications CJ Lukas, FB Yahya, J Breiholz, A Roy, X Chen, HN Patel, NX Liu, ... IEEE Transactions on Biomedical Circuits and Systems 13 (2), 271-281, 2019 | 26 | 2019 |
| A 0.5 V 68 nW ECG monitoring analog front-end for arrhythmia diagnosis A Kosari, J Breiholz, NX Liu, BH Calhoun, DD Wentzloff Journal of Low Power Electronics and Applications 8 (3), 27, 2018 | 23 | 2018 |
| Low-power multicore processor design with reconfigurable same-instruction multiple process Z Yu, Z Yu, X Yu, N Liu, X Zeng IEEE Transactions on Circuits and Systems II: Express Briefs 61 (6), 423-427, 2014 | 22 | 2014 |
| A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V microprocessor using scalable dynamic leakage-suppression logic DS Truesdell, J Breiholz, S Kamineni, N Liu, A Magyar, BH Calhoun IEEE Solid-State Circuits Letters 2 (8), 57-60, 2019 | 21 | 2019 |
| 30.1 A temperature-robust 27.6 nW− 65dBm wakeup receiver at 9.6 GHz X-band P Bassirian, D Duvvuri, DS Truesdell, N Liu, BH Calhoun, SM Bowers 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 460-462, 2020 | 18 | 2020 |
| Design of an S-band nanowatt-level wakeup receiver with envelope detector-first architecture P Bassirian, D Duvvuri, N Liu, D Truesdell, HY Tsao, NS Barker, ... IEEE Transactions on Microwave Theory and Techniques 68 (9), 3920-3929, 2020 | 17 | 2020 |
| A highly reconfigurable bit-level duty-cycled TRF receiver achieving− 106-dBm sensitivity and 33-nW average power consumption J Moody, A Dissanayake, H Bishop, R Lu, N Liu, D Duvvuri, A Gao, ... IEEE Solid-State Circuits Letters 2 (12), 309-312, 2019 | 14 | 2019 |
| A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic HN Patel, A Roy, FB Yahya, N Liu, B Calhoun, K Kumeno, M Yasuda, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 45-48, 2016 | 14 | 2016 |
| A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMINtracking canary sensors A Banerjee, N Liu, HN Patel, BH Calhoun, J Poulton, CT Gray 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 3 | 2017 |
| Design optimization of register file throughput and energy using a virtual prototyping (ViPro) tool N Liu, B Calhoun 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 535-540, 2016 | 2 | 2016 |
| A novel method for accurate measurement and decoupling of SRAM standby leakage Q Dong, Y Ma, H Chen, H Li, Y Jiang, N Liu, W Jian, X Xue, L Chen, ... 2012 IEEE 11th International Conference on Solid-State and Integrated …, 2012 | 2 | 2012 |
| Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing N Liu, Y Jiang, Q Dong, H Li, X Hu, Y Lin 2013 IEEE 10th International Conference on ASIC, 1-4, 2013 | 1 | 2013 |
| A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic HN Patel, A Roy, FB Yahya, N Liu, B Calhoun, A Harada, K Kumeno, ... IEICE Technical Report; IEICE Tech. Rep. 117 (9), 57-61, 2017 | | 2017 |
| 55nm 超低リーク DDC 技術を用いたサブスレッショルド SRAM/Logic 回路 HN Patel, A Roy, FB Yahya, N Liu, B Calhoun 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 117 (9), 57-61, 2017 | | 2017 |
