| A low-cost reliability vs. cost trade-off methodology to selectively harden logic circuits I Wali, B Deveautour, A Virazel, A Bosio, P Girard, M Sonza Reorda Journal of Electronic Testing 33, 25-36, 2017 | 19 | 2017 |
| Towards approximation during test of integrated circuits I Wali, M Traiola, A Virazel, P Girard, M Barbareschi, A Bosio 2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017 | 15 | 2017 |
| An effective hybrid fault-tolerant architecture for pipelined cores I Wali, A Virazel, A Bosio, L Dilillo, P Girard 2015 20th IEEE European test symposium (ETS), 1-6, 2015 | 14 | 2015 |
| Analyzing the impact of the operating system on the reliability of a RISC-V FPGA implementation I Wali, A Sánchez-Macián, A Ramos, JA Maestro 2020 27th IEEE International Conference on Electronics, Circuits and Systems …, 2020 | 13 | 2020 |
| A hybrid fault-tolerant architecture for highly reliable processing cores I Wali, A Virazel, A Bosio, P Girard, S Pravossoudovitch, MS Reorda Journal of Electronic Testing 32, 147-161, 2016 | 11 | 2016 |
| Can we approximate the test of integrated circuits? I Wali, M Traiola, A Virazel, P Girard, M Barbareschi, A Bosio 3rd Workshop On Approximate Computing (WAPCO), 1-7, 2017 | 9 | 2017 |
| Circuit and system fault tolerance techniques I Wali Université Montpellier, 2016 | 8 | 2016 |
| Design space exploration and optimization of a hybrid fault-tolerant architecture I Wali, A Virazel, A Bosio, P Girard, MS Reorda 2015 IEEE 21st International On-Line Testing Symposium (IOLTS), 89-94, 2015 | 5 | 2015 |
| Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults I Wali, A Virazel, A Bosio, L Dilillo, P Girard, A Todri 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 4 | 2014 |
| A low-cost susceptibility analysis methodology to selectively harden logic circuits I Wali, B Deveautour, A Virazel, A Bosio, P Girard, MS Reorda 2016 21th IEEE European Test Symposium (ETS), 1-2, 2016 | 2 | 2016 |
| An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy I Wali, E Casseau, A Tisserand 2017 Conference on Design and Architectures for Signal and Image Processing …, 2017 | 1 | 2017 |
| An Experimental Comparative Study of Fault-Tolerant Architectures I Wali, A Virazel, A Bosio, P Girard VALID: Advances in System Testing and Validation Lifecycle, 1-6, 2015 | 1 | 2015 |
| Présentation du GIP-CNFM-CIME Nanotech A Aitoumeri Abdelhamid Aitoumeri, 2023 | | 2023 |
| A Case Study on the Approximate Test of Integrated Circuits I Wali, A Virazel, P Girard, M Barbareschi, A Bosio AC: Approximate Computing, 2016 | | 2016 |
