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Cited by
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Since 2019
Citations
23
23
h-index
2
2
i10-index
2
2
0
12
6
2021
2022
2023
2024
2
5
11
5
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Co-authors
Enrique G. Marin
Departamento Electrónica y Tecnología de Computadores. Universidad de Granada
Verified email at ugr.es
Sheikh Aamir Ahsan
Nanoelectronics Research & Development Lab, NITSRI
Verified email at nitsri.ac.in
Marta Perucchini, PhD
University of Pisa, KU Leuven
Verified email at ing.unipi.it
Mehak Ashraf Mir
PMRF, PhD scholar, Department of Electronic Systems Engg., Indian Institute of science.
Verified email at iisc.ac.in
Dmitry Polyushkin
Photonics Institute, TU Wien
Verified email at tuwien.ac.at
Thomas Mueller
Vienna University of Technology
Verified email at tuwien.ac.at
Gianluca Fiori
University of Pisa, Italy
Verified email at mercurio.iet.unipi.it
Mike Schwarz
NanoP, THM - University of Applied Sciences
Verified email at ei.thm.de
Alexander Kloes
Professor, Technische Hochschule Mittelhessen
Verified email at ei.thm.de
Tian-Li Wu 吳添立
National Yang Ming Chiao Tung University
Verified email at nycu.edu.tw
Yogesh S. Chauhan
Fellow IEEE, FNAE, Professor-IIT Kanpur
Verified email at iitk.ac.in
Zhen-Hong Huang
National Yang Ming Chiao Tung University; International College of Semiconductor Technology
Verified email at nycu.edu.tw
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Shivendra Kumar Singh
Other names
SK Singh, Shivendra Singh, Shivendra Kumar Kumar Singh
Indian Institute of Technology,Kanpur
Verified email at iitk.ac.in
2D material modeling and simulation
GaN/AlGaN Hemt's and hetrostructures
Reliability Modeling
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Year
A SPICE compact model for ambipolar 2-D-material FETs aiming at circuit design
SA Ahsan, SK Singh, MA Mir, M Perucchini, DK Polyushkin, T Mueller, ...
IEEE Transactions on Electron Devices 68 (6), 3096-3103
, 2021
12
2021
A comprehensive physics-based current–voltage SPICE compact model for 2-D-material-based top-contact bottom-gated Schottky-barrier FETs
SA Ahsan, SK Singh, C Yadav, EG Marin, A Kloes, M Schwarz
IEEE Transactions on Electron Devices 67 (11), 5188-5195
, 2020
11
2020
A Self-Consistent Approach Based on Bayesian Deconvolution for Trapping Time Constant Analysis: A Demonstration to Analyze ΔVTH Transients in p-GaN Gate Power HEMTs
SK Singh, TL Wu, YS Chauhan
IEEE Transactions on Electron Devices
, 2024
2024
Trapping/Detrapping Kinetic Modeling Under Positive/Negative Gate Stress Including Inhibition Dynamics in 4H-SiC MOS Capacitors
SK Singh, BR Chen, ZH Huang, TL Wu, YS Chauhan
IEEE Transactions on Electron Devices 71 (1), 200-205
, 2024
2024
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