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Dr.Suresh kumar Pittala
Dr.Suresh kumar Pittala
Associate Professor of ECE, RVR & JC College of Engineering
Verified email at rvrjc.ac.in
Title
Cited by
Cited by
Year
A novel CMOS G-C complex filter design for multi-mode multi band wireless receiver applications
C Yehoshuva, BNK Reddy, VR Ambati, SK Pittala
Analog Integrated Circuits and Signal Processing 91 (1), 43-51, 2017
72017
Reliability Prediction for Low Power Adiabatic Logic Families
SK Pittala, SP Panchangam, AJ Rani
International Journal of Recent Technology and Engineering (IJRTE) 1 (3 …, 2012
22012
Design of a novel array multiplier using adiabatic logic in 32nm CMOS technology
SK Pittala, A Jhansi Rani
IIOAB Journal 7 (9), 740-745, 2016
12016
A Novel Enhanced Noise-Immunity Design Technique for Dynamic Logic Gates
PS Kumar, UR Bellamkonda, AJ Rani
IOSR-JVSP, 47-54, 2013
12013
Ct and mri image reconstruction based single-path delay feedback (sdf) fft pipeline architecture
R Selvaraj, SK Pittala, S Sadulla, EC Duvvuri
Hellenic Journal οf Radiology 9 (2), 2024
2024
Design and Analysis of Intolerant Approximate Full Adders for Approximate Computing
SM Ramakrishna Kommu, Suresh Kumar Pittala
Design Engineering 2021 (7), 1978-1984, 2021
2021
Direct Matrix Converter Based On Iot Embedded Grid For Implementation And Architecture Of Intelligent FPGA
KV Dr.S.Karthick, Dr. Suresh Kumar Pittala, Ellappan Venugopal, V.Elanangai ...
International Journal of Aquatic Science 1 (1), 193-203, 2021
2021
A CMOS Based Self Repair Fault Tolerant Adder for Low Power Biomedical Systems
SD Suresh Kumar Pittala
Universal Journal of Electrical and Electronic Engineering 7 (6), 307-314, 2020
2020
Fourier Spectrum Features for Face Recognition
ECD Ascar Davix.X, John Moses.C, Suresh Kumar Pittala
International Journal of Innovative Technology and Exploring Engineering …, 2020
2020
Complementary Energy Path Adiabatic Logic-Based Adder Design in 32 Nm FinFET Technology
SK Pittala, A Jhansi Rani
Advances in Communication, Devices and Networking: Proceedings of ICCDN 2017 …, 2018
2018
Low-Power Adiabatic Logic––Design and Implementation in 32-Nanometer Multigate Technology
AJR Suresh Kumar Pittala
Microelectronics, Electromagnetics and Telecommunications Proceedings of …, 2017
2017
Power clock generator design using delay locked loop for adiabatic logic
SK Pittala, AJ Rani
2017 Second International Conference on Electrical, Computer and …, 2017
2017
Robust Pid Design for the Deregulated Power System Using HSA
N Bayati, A Dadkhah
Universitatea" Dunărea de Jos" din Galați, 2017
2017
A NOVEL DESIGN FOR LOW POWER AND LOW LEAKAGE ADIABATIC LOGIC CIRCUIT USING FINFET DEVICE
AJR Suresh Kumar Pittala
Journal of Advanced Research in Dynamical and Control Systems (JARDCS) 9 …, 2017
2017
Design of an Energy Effcient Multiplier Using Complementary Energy Path Adiabatic Logic
SK Pittala, AJ Rani
Universitatea" Dunărea de Jos" din Galați, 2017
2017
Low Power Energy Efficient Multiplier using Adiabatic Logic in 32nm CMOS Technology
AJR Suresh Kumar Pittala
IEEE International Conference on Engineering and Technology (ICET), 170-174, 2016
2016
Design of a Power Clock Generator Using DLL Based Pulse Combiner Circuit for Adiabatic Logic
AJR Suresh Kumar Pittala
Middle-East Journal of Scientific Research 24 (11), 3661-3666, 2016
2016
Proposed Enhanced Noise-Immunity Design Technique for Dynamic Logic Gates
DAJR Suresh Kumar Pittala, Usha Rani Bellamkonda
Third National Conference on Modern Trends in Electronic Communication and …, 2013
2013
A Extensive Active Noise Cancellation from Cardiac Signals using a Constrained Stability Least Mean Square Algorithm
GV N. M. Sai Krishna, P. Suresh Kumar
IJECT 3 (04), 2012
2012
Characterization of Proposed Iterative Hyperbolic Localization Solution using Statistical Studies
EC Duvvuri, VK Minchula, SK Pittala, SR Gottapu
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Articles 1–20