| Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor L Morais, V Silva, A Goldman, C Alvarez, J Bosch, M Frank, G Araujo Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 20 | 2019 |
| Task parallel programming model+ hardware acceleration= performance advantage T Dallou, DCS Lucas, G Araujo, L Morais, EF Barbosa, M Frank, R Bagley, ... 2016 IEEE Hot Chips 28 Symposium (HCS), 1-1, 2016 | 5 | 2016 |
| Using Petri-Net modelling to support the case for HW-assisted task scheduling LH Morais, A Goldman, G Araujo Anais, 2017 | 1 | 2017 |
| Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor L Morais, D Jiménez-González, C Álvarez Barcelona Supercomputing Center, 2022 | | 2022 |
| Adding native support for task scheduling to a Linux-capable RISC-V multicore system LH Morais Universidade de São Paulo, 2019 | | 2019 |
| Task Parallel Programming Model Performance Advantage T Dallou, DCS Lucas, G Araujo, L Morais, EF Barbosa, M Frank, R Bagley, ... | | |
