A Preliminary Review on Novel Coronavirus Disease: COVID-19 JRE Miranji Katta , Satish Rapaka, Ramkumar Adireddi Coronaviruses 1 (1), 90 - 97, 2020 | 4 | 2020 |
An Efficient Learning Model Selection for Dengue Detection M Katta, R Sandanalakshmi, G Srilakshmi, R Adireddi Intelligent and Cloud Computing: Proceedings of ICICC 2021, 439-453, 2022 | 2 | 2022 |
ULTRA LOW POWER LATENCY OPTIMISED EFFICIENT TRNG AR Kumar IEI 52 (6), 2023 | | 2023 |
KIDNEY STONE DETECTION USING DEEP LEARNING TECHNIQUES RA SRINIVASULU PARRE INDUSTRIAL ENGINEERIG JOURNAL 52 (4), 2383-2390, 2023 | | 2023 |
DEEP LEARNING FOR FACE RECOGNITION BASED ON LOG-GABOR AND LBP SP RAMKUMAR ADIREDDI INDUSTRIAL ENGINEERIG JOURNAL 52 (4), 2391-2399, 2023 | | 2023 |
Multi-Threshold Voltage transistor logic and Gate Diffusion Input based ALU for power efficient processors ARK Kondamuri Purna Sidhu Science, Technology and Development 9 (7), 2020 | | 2020 |
Implementation of Triple Data Encryption Standard Architecture VSB A.Ram Kumar, Shaik Mubeena IJSRCSEIT 2 (6), 2017 | | 2017 |
FPGA Implementation of Algorithmic Counter Based Wallace Multiplier RA Sanjeeva Rao.B IJECT 8 (3), 2017 | | 2017 |
Low Power Test Generation by Skewed Load Test Cubes Based on Functional Broadside Tests ARAMK A. PAVANI IJVDCS 4 (7), 2016 | | 2016 |
Design of Novel Programmable PRPG for Low power Applications ARK E. Bala Krishna IJIRSE 2 (9), 2016 | | 2016 |
Design and Implementation of AMBA AXI to AHB Bridge KLSA Ramkumar IJSRD 3 (1), 2015 | | 2015 |
RTL level CED and Correction technique with Run Time adaptability AR E Jagadeeswara Rao IJAEEE 4 (2), 2015 | | 2015 |
Design and Implementation of 32 Bit Unsigned Multiplier Using Conditional Sum Adder ARAMK G.RAJU IJVDCS 2 (9), 2014 | | 2014 |
Design and Implementation of Different Quaternary Signed Digit Adder ARAMK S.GOPI KRISHNA IJVDCS 2 (9), 0899-0905, 2014 | | 2014 |
POWER REDUCTION BY GUARDED EVALUATION CONSIDERING LOGIC ARCHITECTURE AND USING CLOCK GATING ARAMK G. SURESH IJEEE 3 (2), 2013 | | 2013 |