| Delay test generation ER Hsieh, RA Rasmussen, LJ Vidunas, WT Davis Proceedings of the 14th Design Automation Conference, 486-491, 1977 | 175 | 1977 |
| Structure and process of basic complementary logic gate made by junctionless transistors SS Chung, ER Hsieh US Patent App. 13/064,168, 2012 | 148 | 2012 |
| High-density multiple bits-per-cell 1T4R RRAM array with gradual SET/RESET and its effectiveness for deep learning ER Hsieh, M Giordano, B Hodson, A Levy, SK Osekowsky, RM Radway, ... 2019 IEEE International Electron Devices Meeting (IEDM), 35.6. 1-35.6. 4, 2019 | 50 | 2019 |
| Noise in nanoscale semiconductor devices T Grasser Springer Nature, 2020 | 43 | 2020 |
| RADAR: A fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays BQ Le, A Levy, TF Wu, RM Radway, ER Hsieh, X Zheng, M Nelson, ... IEEE Transactions on Electron Devices 68 (9), 4397-4403, 2021 | 34 | 2021 |
| Four-bits-per-memory one-transistor-and-eight-resistive-random-access-memory (1T8R) array ER Hsieh, X Zheng, BQ Le, YC Shih, RM Radway, M Nelson, S Mitra, ... IEEE Electron Device Letters 42 (3), 335-338, 2021 | 27 | 2021 |
| The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect … ER Hsieh, SS Chung Applied Physics Letters 96 (9), 2010 | 24 | 2010 |
| The experimental demonstration of the BTI-induced breakdown path in 28nm high-k metal gate technology CMOS devices ER Hsieh, PY Lu, SS Chung, KY Chang, CH Liu, JC Ke, CW Yang, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 21 | 2014 |
| The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found ER Hsieh, YL Tsai, SS Chung, CH Tsai, RM Huang, CT Tsai 2012 International Electron Devices Meeting, 19.2. 1-19.2. 4, 2012 | 17 | 2012 |
| The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique HM Tsai, ER Hsieh, SS Chung, CH Tsai, RM Huang, CT Tsai, CW Liang 2012 Symposium on VLSI Technology (VLSIT), 189-190, 2012 | 15 | 2012 |
| A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement MH Lin, ER Hsieh, SS Chung, CH Tsai, PW Liu, YH Lin, CT Tsai, GH Ma 2009 Symposium on VLSI Technology, 52-53, 2009 | 15 | 2009 |
| An experimental approach to characterizing the channel local temperature induced by self-heating effect in FinFET ER Hsieh, MR Jiang, JL Lin, SS Chung, TP Chen, SA Huang, TJ Chen, ... IEEE Journal of the Electron Devices Society 6, 866-874, 2018 | 14 | 2018 |
| New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress ER Hsieh, SS Chung, CH Tsai, RM Huang, CT Tsai, CW Liang 2011 International Reliability Physics Symposium, XT. 9.1-XT. 9.2, 2011 | 11 | 2011 |
| A FORMing-Free HfO2-/HfON-Based Resistive-Gate Metal–Oxide–Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory With 3-Bit-Per-Cell … ER Hsieh, KT Chen, PY Chen, SS Wong, SS Chung IEEE Transactions on Electron Devices 68 (6), 2699-2704, 2021 | 10 | 2021 |
| A 14-nm FinFET logic CMOS process compatible RRAM flash with excellent immunity to sneak path ER Hsieh, YC Kuo, CH Cheng, JL Kuo, MR Jiang, JL Lin, HW Chen, ... IEEE Transactions on Electron Devices 64 (12), 4910-4918, 2017 | 10 | 2017 |
| NAND type variable resistance random access memory and methods SS Chung, ER HSIEH US Patent 9,548,398, 2017 | 10 | 2017 |
| The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown ER Hsieh, ZH Huang, SS Chung, JC Ke, CW Yang, CT Tsai, TR Yew 2015 IEEE International Electron Devices Meeting (IEDM), 3.4. 1-3.4. 4, 2015 | 10 | 2015 |
| More strain and less stress-the guideline for developing high-end strained CMOS technologies with acceptable reliability SS Chung, ER Hsieh, DC Huang, CS Lai, CH Tsai, PW Liu, YH Lin, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 9 | 2008 |
| IEEE International Electron Devices Meeting 2008 SS Chung, ER Hsieh, DC Huang, CS Lai, CH Tsai, PW Liu, YH Lin, ... Technical Digest, 435-438, 2008 | 9 | 2008 |
| Embedded PUF on 14nm HKMG FinFET platform: A novel 2-bit-per-cell OTP-based memory feasible for IoT secuirty solution in 5G era ER Hsieh, HW Wang, CH Liu, SS Chung, TP Chen, SA Huang, TJ Chen, ... 2019 Symposium on VLSI Technology, T118-T119, 2019 | 8 | 2019 |
