RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography YM Kuo, F Garcia-Herrero, O Ruano, JA Maestro IEEE Transactions on Computers, 2022 | 11 | 2022 |
Educational design kit for synopsys tools with a set of characterized standard cell library YM Kuo, LJ Arana, L Seva, C Marchese, L Tozzi 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 10 | 2018 |
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors YM Kuo, F Garcia-Herrero, O Ruano, JA Maestro Computers & Electrical Engineering 99, 107759, 2022 | 5 | 2022 |
Versatile RISC-V ISA Galois Field arithmetic extension for cryptography and error-correction codes YM Kuo, F Garcia-Herrero, JA Maestro Fifth Workshop on Computer Architecture Research with RISC-V (CARRV), 2021 | 5 | 2021 |
Analog front-end design of contactless RFID smart card ISO/IEC14443A standard—Compliant YM Kuo, A Grosso, F Galimberti, J Tántera, J Mallo, S Verrastro 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 3 | 2018 |
Evaluación del software uModelFactory como herramienta didáctica N González, L Sugezky, M Prieto, M Giura, Y Kuo, M Trujillo, JM Cruz 2016 IEEE Biennial Congress of Argentina (ARGENCON), 1-5, 2016 | 3 | 2016 |
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-based RISC-V SoCs using RISC-V Vector Extension YM Kuo, MF Flanagan, F Garcia-Herrero, O Ruano, JA Maestro IEEE Transactions on Aerospace and Electronic Systems, 2023 | 2 | 2023 |
Desarrollo del front-end de un transceptor RFID pasivo bajo proceso CMOS de 500 nm A Grosso, F Galimberti, JA Tántera, YM Kuo, J Rodriguez Mallo FRBA - Revista Proyecciones 15 (2), 77-92, 2017 | 1 | 2017 |
Evaluation of the uModel factory software used for the modeling of embedded systems with concurrent states M Prieto, L Sugezky, N González, M Giura, Y Kuo, M Trujillo, JM Cruz 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017 | 1 | 2017 |
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration JL Imaña, L Piñuel, YM Kuo, O Ruano, F García-Herrero IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
Design, Implementation, and Characterization of Custom RISC-V Soft-Core Processors for Future Communication Networks YM Kuo Universidad Antonio de Nebrija, 2022 | | 2022 |
Desarrollo de un circuito integrado transmisor RFID pasivo A Grosso, F Galimberti, YM Kuo, F Aguirre, S Pazos, J Rodríguez Mallo, ... FRBA - Revista Proyecciones 15 (1), 75-96, 2017 | | 2017 |
DESARROLLO DEL FRONT-END ANALÓGICO RFID Y UN BANCO DE PRUEBA BASADO EN EL ESTÁNDAR ISO/IEC 14443 YM Kuo, A Grosso, F Galimberti, J Tántera | | |