| A modified high speed and less area BCD adder architecture using Mirror adder YD Ykuntam, SH Prasad 2021 2nd International Conference on Smart Electronics and Communication …, 2021 | 3 | 2021 |
| Enhancing performance of dual-gate FinFET with high-K gate dielectric materials in 5 nm technology: a simulation study MVG Rao, N Ramanjaneyulu, B Pydi, U Soma, KR Babu, SH Prasad Transactions on Electrical and Electronic Materials 24 (6), 557-569, 2023 | 1 | 2023 |
| Review in Low Power VLSI Design SH Prasad, G Rama Naidu, G Ajay Shankar, SBG Tilak Babu International Journal of Research [Sl] 4 (5), 1121-1135, 2017 | 1 | 2017 |
| An efficient Pulse Doppler Radar block level modeling with Xilinx System Generator B Penumutchi, HP Satti, Y Ykuntam 2022 2nd International Conference on Artificial Intelligence and Signal …, 2022 | | 2022 |
| Execution Analysis of Machine Learning Technique Based Detection and Classification of Brain Tumor from MRI images SH Prasad, J Gandeti, BS Sridevi, M Neeladri, GA Sankar, K Pavani 2022 First International Conference on Electrical, Electronics, Information …, 2022 | | 2022 |
| kogge stone adder with GDI technique in 130 mm technology for high performance DSP applications 2017 international conference on smart technologies for smart nation, 2017 | | 2017 |
| Efficient Power and Area Reduction Codec for Error Detection Scheme Using Enhanced Clock Gating Technique S prasad International Journal of Engineering Research and Applications (IJERA) 3 (4 …, 2013 | | 2013 |
| Designing An Area Efficient And Power Optimized Codec For Error Detection Scheme Using Enhanced Clock Gating Technique International Journal of Engineering Research & Technology (IJERT) 2 (Issue 6), 2013 | | 2013 |
