| Test volume and application time reduction through scan chain concealment I Bayraktaroglu, A Orailoglu, A Orailoglu Proceedings of the 38th annual Design Automation Conference, 151-155, 2001 | 243 | 2001 |
| Flow graph representation A Orailoglu, DD Gajski 23rd ACM/IEEE Design Automation Conference, 503-509, 1986 | 107 | 1986 |
| Architectures for silicon nanoelectronics and beyond RI Bahar, D Hammerstrom, J Harlow, WH Joyner, C Lau, D Marculescu, ... Computer 40 (1), 25-33, 2007 | 99 | 2007 |
| Reducing test application time through test data mutation encoding S Reda, A Orailoglu Proceedings of the conference on Design, automation and test in Europe, 387, 2002 | 89 | 2002 |
| Test power reduction through minimization of scan chain transitions O Sinanoglu, I Bayraktaroglu, A Orailoglu Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 166-171, 2002 | 84 | 2002 |
| Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression I Bayraktaroglu, A Orailoglu Proceedings. 21st VLSI Test Symposium, 2003., 113-118, 2003 | 73 | 2003 |
| Automatic synthesis of self-recovering VLSI systems A Orailoglu, R Karri IEEE Transactions on Computers 45 (2), 131-142, 1996 | 67 | 1996 |
| Test application time and volume compression through seed overlapping W Rao, I Bayraktaroglu, A Orailoglu Proceedings of the 40th annual Design Automation Conference, 732-737, 2003 | 63 | 2003 |
| CircularScan: a scan architecture for test cost reduction B Arslan, A Orailoglu Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 60 | 2004 |
| Concurrent application of compaction and compression for test time and data volume reduction in scan designs I Bayraktaroglu, A Orailoglu IEEE Transactions on Computers 52 (11), 1480-1489, 2003 | 60 | 2003 |
| Microarchitectural synthesis of performance-constrained, low-power VLSI designs L Goodby, A Orailoglu, PM Chau Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994 | 60 | 1994 |
| Microarchitectural synthesis of VLSI designs with high test concurrency IG Harris, A Orailoglu 31st Design Automation Conference, 206-211, 1994 | 59 | 1994 |
| Low-power instruction bus encoding for embedded processors P Petrov, A Orailoglu IEEE transactions on very large scale integration (VLSI) systems 12 (8), 812-826, 2004 | 56 | 2004 |
| A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses R Ayoub, A Orailoglu Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 55 | 2005 |
| A novel scan architecture for power-efficient, rapid test [sequential circuits] O Sinanoglu, A Orailoglu IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002 …, 2002 | 53 | 2002 |
| Performance analysis and optimization of asynchronous circuits P Kudva, G Gopalakrishnan, E Brunvand, V Akella Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994 | 52* | 1994 |
| Modeling scan chain modifications for scan-in test power minimization O Sinanoglu, A Orailoglu ITC, 602-611, 2003 | 50 | 2003 |
| Scan power reduction through test data transition frequency analysis O Sinanoglu, I Bayraktaroglu, A Orailoglu Proceedings. International Test Conference, 844-850, 2002 | 49 | 2002 |
| Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures A Orailoglu, R Karri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (3), 304-311, 1994 | 47 | 1994 |
| Test cost minimization through adaptive test development M Chen, A Orailoglu 2008 IEEE International Conference on Computer Design, 234-239, 2008 | 42 | 2008 |
