| Clock generation and distribution for the first IA-64 microprocessor S Tam, S Rusu, UN Desai, R Kim, J Zhang, I Young IEEE Journal of Solid-State Circuits 35 (11), 1545-1552, 2000 | 302 | 2000 |
| A 65-nm dual-core multithreaded Xeon® processor with 16-MB L3 cache S Rusu, S Tam, H Muljono, D Ayers, J Chang, B Cherkauer, J Stinson, ... IEEE Journal of Solid-State Circuits 42 (1), 17-25, 2006 | 279* | 2006 |
| A 45 nm 8-core enterprise Xeon processor S Rusu, S Tam, H Muljono, J Stinson, D Ayers, J Chang, R Varada, ... IEEE Journal of Solid-State Circuits 45 (1), 7-14, 2009 | 239 | 2009 |
| Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system S Rusu, DJ Ayers, JS Burns US Patent 7,111,178, 2006 | 211 | 2006 |
| Multiple mode power throttle mechanism JS Burns, S Rusu, DJ Ayers, ET Grochowski, M Eng, V Tiwari US Patent 6,931,559, 2005 | 133 | 2005 |
| Apparatus for thermal management of multiple core microprocessors S Rusu, SM Tam US Patent 6,908,227, 2005 | 133 | 2005 |
| The 65-nm 16-MB shared on-die L3 cache for the dual-core Intel Xeon processor 7100 series J Chang, M Huang, J Shoemaker, J Benoit, SL Chen, W Chen, S Chiu, ... IEEE Journal of Solid-State Circuits 42 (4), 846-852, 2007 | 131 | 2007 |
| VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors SM Tam, S Rusu US Patent 6,762,629, 2004 | 112 | 2004 |
| A 7-nm 4-GHz Arm¹-core-based CoWoS¹ chiplet design for high-performance computing MS Lin, TC Huang, CC Tsai, KH Tam, KCH Hsieh, CF Chen, WH Huang, ... IEEE Journal of Solid-State Circuits 55 (4), 956-966, 2020 | 101 | 2020 |
| The first IA-64 microprocessor S Rusu, G Singer IEEE Journal of Solid-State Circuits 35 (11), 1539-1544, 2000 | 97 | 2000 |
| Semiconductor-on-insulator resistor-capacitor circuit H Muljono, S Rusu US Patent 6,707,118, 2004 | 94 | 2004 |
| Adaptive variable frequency clock system for high performance low power microprocessors SM Tam, S Rusu US Patent 6,608,528, 2003 | 93* | 2003 |
| Passive components in vias in a stacked integrated circuit package S Sharan, R Mahajan, S Rusu, DS Gardner US Patent 10,236,209, 2019 | 84 | 2019 |
| Clock generation and distribution for the first IA-64 microprocessor S Rusu, S Tam 2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000 | 77 | 2000 |
| Trends and challenges in VLSI technology scaling towards 100 nm S Rusu, M Sachdev, C Svensson, B Nauta Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 72 | 2002 |
| Digital throttle for multiple operating points JS Burns, S Rusu, DJ Ayers, ET Grochowski, M Eng, V Tiwari US Patent 7,281,140, 2007 | 71 | 2007 |
| Integrated passive components in a stacked integrated circuit package S Rusu, D Gardner US Patent App. 14/777,434, 2016 | 69 | 2016 |
| Method and apparatus for analyzing the power network of a VLSI circuit S Rusu, CL Yee US Patent 5,598,348, 1997 | 64 | 1997 |
| 5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family S Rusu, H Muljono, D Ayers, S Tam, W Chen, A Martin, S Li, S Vora, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 61 | 2014 |
| Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load S Rusu, DJ Ayers, JS Burns US Patent 7,464,276, 2008 | 61 | 2008 |
