Design of 32Bit Carry-lookahead Adder using Constant Delay Logic K Santosh, SG Ramesh Network 25, 0, 2014 | 2* | 2014 |
A 2.4 GHz LNA Design for 802.11 WLAN Applications DS Babu, MM Reddy, G Ramesh, DS Babu, SMS Daula, GA Khan 2021 5th Conference on Information and Communication Technology (CICT), 1-5, 2021 | 1 | 2021 |
Self Balancing Personal Transporter GR ,Kousar B Thaseen | 1* | |
Empirical Analysis of Artificial limb for Trans Radial Amputation People with the support of advanced machine learning strategies. GA Khan, SM Daula, G Ramesh, SM Reddy International Journal of Early Childhood Special Education 14 (5), 2022 | | 2022 |
Innovative Design of 64bit Processing Unit with a Clock Gating Technique VS Keerthi, G Ramesh Design Engineering, 1624-1632, 2021 | | 2021 |
IOT BASED REAL–TIME LOCATING SYSTEM FOR ASSET MANEGEMENT USING ACTIVE RFID N YESHASWINI, SRIG RAMESH Solid State Technology, 4366-4375, 2020 | | 2020 |
Implementation of High Performance Multiple Asset Tracking using UHF RFID in Supply Chain Management DBR G.Ramesh Test Engineering And Management 82, 11416-11420, 2020 | | 2020 |
‘Design of Low Power Hybrid Gaincell-e DRAM for Embedded Processors’ GVKG Ramesh ‘International Journal of Engineering and Advanced Technology (IJEAT)’, 8 (6 …, 2019 | | 2019 |
A system for Managing Power Conductors MMR G.Ramesh,Dr.S.M.ShamsheerDaula IN Patent 43,310, 2018 | | 2018 |
Probability-Driven Multi Bit Flip-Flop Design Optimization with Clock Gating CDVG Ramesh Jour of Adv Research in Dynamical & Control Systems 10 (5), 32-41, 2018 | | 2018 |
Design of Hybrid LUT/MUX Based Configurable Logic Architectures for FPGAs MDKG Ramesh International Journal of Research 4 (10), 285-291, 2017 | | 2017 |
Improve the Memory Fault Detection Efficiency Based on Difference-Set Codes KR THEERTHA, G RAMESH | | 2014 |
Efficient Key data list for Enhancing Symmetric Read-Write Page Access DSMS Daula | | |
Randomized Partially-Minimal Routing Architecture for 3-D Mesh Network on Chips BRS Reddy, G Ramesh | | |
DESIGN OF A LOW POWER FIXED WIDTH REPLICA REDUNDANCY BLOCK BASED MULTIPLIER NR Reddy, G Ramesh | | |