| A partially static high frequency 18t hybrid topological flip-flop design for low power application AK Mishra, U Chopra, D Vaithiyanathan IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 1592-1596, 2021 | 21 | 2021 |
| Performance Analysis of Non-Identical Master. Slave Flip Flops at 65nm Node. U Chopra, AK Mishra, D Vaithiyanathan International Journal of Innovative Technology and Exploring Engineering …, 2019 | 12 | 2019 |
| Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application A Kumar Mishra, D Vaithiyanathan, U Chopra International Journal of Circuit Theory and Applications, 2021 | 11 | 2021 |
| Power consumption and delay comparison of a modified tcff with existing ff implemented using finfet and load test circuit analysis D Vaithiyanathan, AK Mishra, T Bhardwaj, VJ Verma, B Kaur 2021 IEEE Madras Section Conference (MASCON), 1-5, 2021 | 7 | 2021 |
| Design and mathematical analysis of a 7t sram cell with enhanced read snm using pmos as an access transistor AK Mishra, Y Pal, B Kaur Circuit World 48 (3), 322-332, 2022 | 4 | 2022 |
| Performance Analysis of 8-Point Approximate DCT Architecture Using Conventional and Hybrid Adders D Vaithiyanathan, R Kolhe, AK Mishra, PJ Britto, K Kunaraj 2020 IEEE International Symposium on Smart Electronic Systems (iSES …, 2021 | 4 | 2021 |
| Review of Different Flip-Flop Circuits and a Modified Flip-Flop Circuit for Low Voltage Operation VJ Verma, AK Mishra, D Vaithiyanathan, B Kaur 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT), 1-5, 2022 | 3 | 2022 |
| Performance Analysis of a High-Speed High-Precision Dynamic Comparator V Dhandapani, A Mishra, A Kumar, AK Mishra, S Singh, B Kaur Indian Journal of Pure & Applied Physics (IJPAP) 60 (3), 238-245, 2022 | 3 | 2022 |
| Study and Implementation of Low Power Decoder using DVL and TGL Logic AK Mishra, S Sinha, DDV Subbarao, D Vaithiyanathan, B Kaur 2021 IEEE Madras Section Conference (MASCON), 1-6, 2021 | 3 | 2021 |
| A novel approach for noise tolerant energy efficient TSPC dynamic circuit design P Verma, AK Sharma, A Noor, AK Mishra, VS Pandey Analog Integrated Circuits and Signal Processing 100, 119-131, 2019 | 3 | 2019 |
| Design of Low Power N-Bridge Master and P-Bridge Slave Topologically Arranged Flip-Flop S Shukla, AK Mishra, P Verma, D Vaithiyanathan, B Kaur 2022 International Conference on Smart Generation Computing, Communication …, 2022 | 2 | 2022 |
| A low power high speed single phase clock level restoring 16T master-slave flip-flop AK Mishra, U Chopra, B Kaur Circuit World, 2022 | 2 | 2022 |
| Comparative Analysis of Preamplifiers for Comparators. A Mishra, V Dhandapani, S Singh, S Sonar, AK Mishra Journal of Engineering Research (2307-1877), 2022 | 2 | 2022 |
| Implementation and investigation of different sram cells using dltfet device AK Mishra, S Sinha, DDV Subbarao, D Vaithiyanathan, B Kaur 2021 IEEE Madras Section Conference (MASCON), 1-6, 2021 | 2 | 2021 |
| Implementation and Analysis of Couple Suppress Current Sense Amplifier at 45nm and 65nm Regime AK Mishra, S Pal, D Vaithiyanathan 2021 Sixth IEEE International Conference on Wireless Communications, Signal …, 2021 | 2 | 2021 |
| An Energy-Efficient Conditional-Boosting Flip-Flop with Conditional Pulse for Low Power Application D Patidar, AK Mishra, D Vaithiyanathan, B Kaur 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT), 1-7, 2022 | 1 | 2022 |
| Implementation and Analysis of Efficient Low Power Dynamic Circuit Technique P Verma, AK Mishra 2021 IEEE 2nd International Conference on Smart Electronics and …, 2021 | 1 | 2021 |
| Comparative analysis in terms of power and delay of the different sense amplifier topologies AK Mishra, U Chopra, D Vaithiyanathan Journal of Engineering Research -, https://doi.org/10.36909/jer.EMSME.13841, 2021 | 1 | 2021 |
| Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit S Sharma, S Kumar, A Kumar Mishra, D Vaithiyanathan, B Kaur Advanced Science, Engineering and Medicine 12 (10), 1289-1295, 2020 | 1 | 2020 |
| Performance Analysis of Implicit Pulsed and Low-Glitch Power-Efficient Double-Edge-Triggered Flip-Flops Using C-Elements D Vaithiyanathan, V Gupta, S Kumar, AK Mishra, J Britto Pari International Conference on Communication, Computing and Electronics Systems …, 2020 | 1 | 2020 |
Vaithiyanathan DhandapaniNational Institute of Technology DelhiVerified email at nitdelhi.ac.in
