| A 13.7 TFLOPS/W floating-point DNN processor using heterogeneous computing architecture with exponent-computing-in-memory J Lee, J Kim, W Jo, S Kim, S Kim, J Lee, HJ Yoo 2021 Symposium on VLSI Circuits, 1-2, 2021 | 32 | 2021 |
| A 36.2 dB high SNR and PVT/leakage-robust eDRAM computing-in-memory macro with segmented BL and reference cell array S Ha, S Kim, D Han, S Um, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 69 (5), 2433-2437, 2022 | 18 | 2022 |
| PNNPU: A 11.9 TOPS/W high-speed 3D point cloud-based neural network processor with block-based point processing for regular DRAM access S Kim, J Lee, D Im, HJ Yoo 2021 Symposium on VLSI Circuits, 1-2, 2021 | 18 | 2021 |
| Neuro-cim: A 310.4 tops/w neuromorphic computing-in-memory processor with low wl/bl activity and digital-analog mixed-mode neuron firing S Kim, S Kim, S Um, S Kim, K Kim, HJ Yoo 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 16 | 2022 |
| An overview of sparsity exploitation in CNNs for on-device intelligence with software-hardware cross-layer optimizations S Kang, G Park, S Kim, S Kim, D Han, HJ Yoo IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (4 …, 2021 | 14 | 2021 |
| OmniDRL: A 29.3 TFLOPS/W deep reinforcement learning processor with dualmode weight compression and on-chip sparse weight transposer J Lee, S Kim, S Kim, W Jo, D Han, J Lee, HJ Yoo 2021 Symposium on VLSI Circuits, 1-2, 2021 | 12 | 2021 |
| C-DNN: A 24.5-85.8 TOPS/W complementary-deep-neural-network processor with heterogeneous CNN/SNN core architecture and forward-gradient-based sparsity generation S Kim, S Kim, S Hong, S Kim, D Han, HJ Yoo 2023 IEEE International Solid-State Circuits Conference (ISSCC), 334-336, 2023 | 11 | 2023 |
| A 64.1 mW accurate real-time visual object tracking processor with spatial early stopping on siamese network S Kim, S Kim, S Kim, D Han, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1675-1679, 2021 | 11 | 2021 |
| Gst: Group-sparse training for accelerating deep reinforcement learning J Lee, S Kim, S Kim, W Jo, HJ Yoo arXiv preprint arXiv:2101.09650, 2021 | 10 | 2021 |
| An energy-efficient GAN accelerator with on-chip training for domain-specific optimization S Kim, S Kang, D Han, S Kim, S Kim, HJ Yoo IEEE Journal of Solid-State Circuits 56 (10), 2968-2980, 2021 | 9 | 2021 |
| ECIM: exponent computing in memory for an energy-efficient heterogeneous floating-point DNN training processor J Lee, J Kim, W Jo, S Kim, S Kim, HJ Yoo IEEE Micro 42 (1), 99-107, 2021 | 9 | 2021 |
| A low-power graph convolutional network processor with sparse grouping for 3d point cloud semantic segmentation in mobile devices S Kim, S Kim, J Lee, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4), 1507-1518, 2022 | 8 | 2022 |
| 16.5 dynaplasia: An edram in-memory-computing-based reconfigurable spatial accelerator with triple-mode cell for dynamic resource switching S Kim, Z Li, S Um, W Jo, S Ha, J Lee, S Kim, D Han, HJ Yoo 2023 IEEE International Solid-State Circuits Conference (ISSCC), 256-258, 2023 | 7 | 2023 |
| 2.7 MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices D Han, J Ryu, S Kim, S Kim, HJ Yoo 2023 IEEE International Solid-State Circuits Conference (ISSCC), 50-52, 2023 | 6 | 2023 |
| A 709.3 TOPS/W event-driven smart vision SoC with high-linearity and reconfigurable MRAM PIM W Xie, H Sang, B Kwon, D Im, S Kim, S Kim, HJ Yoo 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 5 | 2023 |
| SNPU: Always-on 63.2 μW Face Recognition Spike Domain Convolutional Neural Network Processor with Spike Train Decomposition and Shift-and-Accumulation Unit S Kim, S Kim, S Um, S Kim, J Lee, HJ Yoo 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2-4, 2022 | 5 | 2022 |
| An 0.92 mj/frame high-quality fhd super-resolution mobile accelerator soc with hybrid-precision and energy-efficient cache Z Li, S Kim, D Im, D Han, HJ Yoo 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 5 | 2022 |
| A 43.1 tops/w energy-efficient absolute-difference-accumulation operation computing-in-memory with computation reuse S Um, S Kim, S Kim, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1605-1609, 2021 | 5 | 2021 |
| DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell S Kim, Z Li, S Um, W Jo, S Ha, J Lee, S Kim, D Han, HJ Yoo IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices W Jo, S Kim, J Lee, D Han, S Kim, S Choi, HJ Yoo 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 3 | 2023 |
Donghyeon HanMIT Postdoctoral AssociateVerified email at mit.edu
