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Suman Lata Tripathi
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A review on performance comparison of advanced MOSFET structures below 45 nm technology node
N Mendiratta, SL Tripathi
Journal of Semiconductors 41 (6), 1-10, 2020
632020
Low leakage pocket junction-less DGTFET with biosensing cavity region
SL Tripathi, R Patel, VK Agrawal
Turkish Journal of Electrical Engineering and Computer science 27 (4), 2466-2474, 2019
372019
18nm n-channel and p-channel Dopingless asymmetrical Junctionless DG-MOSFET: low power CMOS based digital and memory applications
N Mendiratta, SL Tripathi
Silicon 14 (11), 6435-6446, 2022
352022
Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications
N Mendiratta, SL Tripathi, S Padmanaban, E Hossain
Applied Sciences 10 (7), 2499, 2020
342020
Multi-gate MOSFET structures with high-k dielectric materials
SL Tripathi, R Mishra, RA Mishra
J. Electron Devices 16, 1388-1394, 2012
332012
Characteristic comparison of connected DG FINFET, TG FINFET and Independent Gate FINFET on 32 nm technology
SL Tripathi, R Mishra, RA Mishra
2012 2nd International Conference on Power, Control and Embedded Systems, 1-7, 2012
302012
A journey from bulk MOSFET to 3 nm and beyond
A Samal, SL Tripathi, SK Mohapatra
Transactions on Electrical and Electronic Materials 21 (5), 443-455, 2020
292020
Comprehensive analysis of 7T SRAM cell architectures with 18nm FinFET for low power bio-medical applications
TS Kumar, SL Tripathi
Silicon 14 (10), 5213-5224, 2022
262022
Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology
SL Tripathi, GS Patel
Wireless Personal Communications, 1-10, 2019
262019
Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique
TS Kumar, SL Tripathi
Wireless Personal Communications, https://doi.org/10.1007/s11277-020-07765, 2020
252020
Low-Power Efficient p+ Si0.7Ge0.3 Pocket Junctionless SGTFET with Varying Operating Conditions
SL Tripathi, SK Sinha, GS Patel
Journal of Electronic Materials 49 (7), 4291-4299, 2020
232020
Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications
S Verma, SL Tripathi, M Bassi
2019 Devices for Integrated Circuit (DevIC), 10.1109/DEVIC.2019.8783754, 2019
232019
SBOX under PVT variation
A Kumar, SL Tripathi
Analog Integr Circ Sig Process 105, 73-82, 2020
22*2020
A boosted chimp optimizer for numerical and engineering design optimization challenges
CL Kumari, VK Kamboj, SK Bath, SL Tripathi, M Khatri, S Sehgal
Engineering with computers 39 (4), 2463-2514, 2023
182023
Implementation of CMOS SRAM Cells in 7, 8, 10 and12-Transistor Topologies and their Performance Comparison
TS Kumar, SL Tripathi
International Journal of Engineering and Advanced Technology (IJEAT) 8 (2s2 …, 2019
182019
High performance Bulk FinFET with bottom spacer
SL Tripathi, R Mishra, V Narendra, RA Mishra
2013 IEEE International Conference on Electronics, Computing and …, 2013
182013
Effect of Mole fraction and Fin Material on Performance Parameter of 14 nm Heterojunction Si1-xGex FinFET and Application as an Inverter
S Verma, SL Tripathi
Silicon 14 (14), 8793-8804, 2022
172022
Performance Enhanced Unsymmetrical FinFET and its Applications
GS Patel, SL Tripathi, S Awasthi
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 222-227, 2018
172018
Process evaluation in FinFET based 7T SRAM cell
TS Kumar, SL Tripathi
Analog Integrated Circuits and Signal Processing 109 (3), 545-551, 2021
152021
Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm
S Bhattacharya, SL Tripathi, VK Kamboj
Engineering with Computers 39 (2), 1415-1458, 2023
142023
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