| A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs O Ruano, JA Maestro, P Reviriego IEEE Transactions on Nuclear Science 56 (4), 2091-2102, 2009 | 84 | 2009 |
| New protection techniques against SEUs for moving average filters in a radiation environment P Reyes, P Reviriego, JA Maestro, O Ruano IEEE Transactions on Nuclear Science 54 (4), 957-964, 2007 | 71 | 2007 |
| A simulation platform for the study of soft errors on signal processing circuits through software fault injection O Ruano, JA Maestro, P Reyes, P Reviriego 2007 IEEE International Symposium on Industrial Electronics, 3316-3321, 2007 | 23 | 2007 |
| Efficient protection techniques against SEUs for adaptive filters: An echo canceller case study P Reviriego, JA Maestro, O Ruano IEEE Transactions on Nuclear Science 55 (3), 1700-1707, 2008 | 22 | 2008 |
| A fast and efficient technique to apply selective TMR through optimization O Ruano, JA Maestro, P Reviriego Microelectronics Reliability 51 (12), 2388-2401, 2011 | 15 | 2011 |
| RISC-V Galois field ISA extension for non-binary error-correction codes and classical and post-quantum cryptography YM Kuo, F García-Herrero, O Ruano, JA Maestro IEEE Transactions on Computers 72 (3), 682-692, 2022 | 11 | 2022 |
| Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial Ó Ruano, F García-Herrero, LA Aranda, A Sánchez-Macián, L Rodriguez, ... Sensors 21 (4), 1392, 2021 | 11 | 2021 |
| Performance analysis and improvements for a simulation-based fault injection platform O Ruano, JA Maestro, P Reviriego 2008 IEEE International Symposium on Industrial Electronics, 2299-2304, 2008 | 11 | 2008 |
| Automatic insertion of selective TMR for SEU mitigation O Ruano, P Reviriego, JA Maestro 2008 European Conference on Radiation and Its Effects on Components and …, 2008 | 10 | 2008 |
| An efficient technique to protect serial shift registers against soft errors P Reviriego, O Ruano, MF Flanagan, S Pontarelli, JA Maestro IEEE Transactions on Circuits and Systems II: Express Briefs 60 (8), 512-516, 2013 | 9 | 2013 |
| Implementing concurrent error detection in infinite-impulse-response filters P Reviriego, O Ruano, JA Maestro IEEE Transactions on Circuits and Systems II: Express Briefs 59 (9), 583-586, 2012 | 9 | 2012 |
| A new EDAC technique against soft errors based on pulse detectors O Ruano, P Reviriego, JA Maestro 2008 IEEE International Symposium on Industrial Electronics, 2293-2298, 2008 | 8 | 2008 |
| A new protection technique for finite impulse response (FIR) filters in the presence of soft errors P Reyes, P Reviriego, JA Maestro, O Ruano 2007 IEEE International Symposium on Industrial Electronics, 3328-3333, 2007 | 8 | 2007 |
| Design and implementation of efficient QCA full-adders using fault-tolerant majority gates JA Bravo-Montes, A Martín-Toledano, A Sánchez-Macián, O Ruano, ... The Journal of Supercomputing 78 (6), 8056-8080, 2022 | 6 | 2022 |
| Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study JA Maestro, P Reviriego, P Reyes, O Ruano Integration 42 (2), 128-136, 2009 | 6 | 2009 |
| Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors YM Kuo, F Garcia-Herrero, O Ruano, JA Maestro Computers and Electrical Engineering 99, 107759, 2022 | 5 | 2022 |
| An experimental analysis of SEU sensitiveness on system knowledge-based hardening techniques O Ruano, P Reyes, JA Maestro, L Sterpone, P Reviriego 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-6, 2007 | 5 | 2007 |
| Validation and optimization of TMR protections for circuits in radiation environments O Ruano, JA Maestro, P Reviriego 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011 | 4 | 2011 |
| Integration of a real-time ccsds 410.0-b-32 error-correction decoder on fpga-based risc-v socs using risc-v vector extension YM Kuo, MF Flanagan, F Garcia-Herrero, Ó Ruano, JA Maestro IEEE Transactions on Aerospace and Electronic Systems, 2023 | 2 | 2023 |
| Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs LA Aranda, O Ruano, F Garcia-Herrero, JA Maestro IEEE Access 9, 140676-140685, 2021 | 2 | 2021 |
