| Aging-aware lifetime enhancement for memristor-based neuromorphic computing S Zhang, GL Zhang, B Li, HH Li, U Schlichtmann 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 58 | 2019 |
| TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing GL Zhang, B Li, B Yu, DZ Pan, U Schlichtmann 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 91-96, 2018 | 57 | 2018 |
| Statistical training for neuromorphic computing using memristor-based crossbars considering process variations and noise Y Zhu, GL Zhang, T Wang, B Li, Y Shi, TY Ho, U Schlichtmann 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 51 | 2020 |
| Countering variations and thermal effects for accurate optical neural networks Y Zhu, GL Zhang, B Li, X Yin, C Zhuo, H Gu, TY Ho, U Schlichtmann Proceedings of the 39th International Conference on Computer-Aided Design, 1-7, 2020 | 46 | 2020 |
| Lifetime enhancement for rram-based computing-in-memory engine considering aging and thermal effects S Zhang, GL Zhang, B Li, HH Li, U Schlichtmann 2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020 | 34 | 2020 |
| Ferroelectric ternary content addressable memories for energy-efficient associative search X Yin, Y Qian, M Imani, K Ni, C Li, GL Zhang, B Li, U Schlichtmann, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 26 | 2022 |
| EffiTest: Efficient delay test and statistical prediction for configuring post-silicon tunable buffers GL Zhang, B Li, U Schlichtmann Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 25 | 2016 |
| Design-phase buffer allocation for post-silicon clock binning by iterative learning GL Zhang, B Li, J Liu, Y Shi, U Schlichtmann IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 24 | 2017 |
| PathDriver+: Enhanced path-driven architecture design for flow-based microfluidic biochips X Huang, Y Pan, GL Zhang, B Li, W Guo, TY Ho, U Schlichtmann IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 22 | 2021 |
| Sampling-based buffer insertion for post-silicon yield improvement under process variability GL Zhang, B Li, U Schlichtmann 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 22 | 2016 |
| PieceTimer: A holistic timing analysis framework considering setup/hold time interdependency using a piecewise model GL Zhang, B Li, U Schlichtmann 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 21 | 2016 |
| PathDriver: A path-driven architectural synthesis flow for continuous-flow microfluidic biochips X Huang, Y Pan, GL Zhang, B Li, W Guo, TY Ho, U Schlichtmann Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 20 | 2020 |
| Machine learning in advanced IC design: A methodological survey T Chen, GL Zhang, B Yu, B Li, U Schlichtmann IEEE Design & Test 40 (1), 17-33, 2022 | 19 | 2022 |
| Reliable memristor-based neuromorphic design using variation-and defect-aware training D Gaol, GL Zhang, X Yin, B Li, U Schlichtmann, C Zhuo 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 19 | 2021 |
| Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units GL Zhang, B Li, M Hashimoto, U Schlichtmann Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 19 | 2018 |
| Bayesian inference based robust computing on memristor crossbar D Gao, Q Huang, GL Zhang, X Yin, B Li, U Schlichtmann, C Zhuo 2021 58th ACM/IEEE Design Automation Conference (DAC), 121-126, 2021 | 18 | 2021 |
| EffiTest2: Efficient delay test and prediction for post-silicon clock skew configuration under process variations GL Zhang, B Li, Y Shi, J Hu, U Schlichtmann IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 18 | 2018 |
| Energy-aware designs of ferroelectric ternary content addressable memory Y Qian, Z Fan, H Wang, C Li, M Imani, K Ni, GL Zhang, B Li, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 15 | 2021 |
| TimingCamouflage+: Netlist security enhancement with unconventional timing GL Zhang, B Li, M Li, B Yu, DZ Pan, M Brunner, G Sigl, U Schlichtmann IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 14 | 2020 |
| Correctnet: Robustness enhancement of analog in-memory computing for neural networks by error suppression and compensation A Eldebiky, GL Zhang, G Böcherer, B Li, U Schlichtmann 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 11 | 2023 |
