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Kai-Chiang Wu
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Year
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
KC Wu, D Marculescu
Design, Automation, and Test in Europe (DATE) Conference & Exhibition, 75-80, 2009
1242009
Aging-aware timing analysis and optimization considering path sensitization
KC Wu, D Marculescu
Design, Automation, and Test in Europe (DATE) Conference & Exhibition, 1572-1577, 2011
872011
Soft error rate reduction using redundancy addition and removal
KC Wu, D Marculescu
Asia and South Pacific Design Automation Conference (ASP-DAC), 559-564, 2008
402008
A low-cost, systematic methodology for soft error robustness of logic circuits
KC Wu, D Marculescu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 367-379, 2013
392013
Process variability-aware transient fault modeling and analysis
N Miskov-Zivanov, KC Wu, D Marculescu
International Conference on Computer-Aided Design (ICCAD), 685-690, 2008
362008
Power-aware soft error hardening via selective voltage scaling
KC Wu, D Marculescu
International Conference on Computer Design (ICCD), 301-306, 2008
322008
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
KC Wu, D Marculescu, MC Lee, SC Chang
International Symposium on Low Power Electronics and Design (ISLPED), 139-144, 2011
242011
Highly Uniform All‐Vacuum‐Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing
LW Chen, WC Wang, SH Ko, CY Chen, CT Hsu, FC Chiao, TW Chen, ...
Advanced Intelligent Systems 3 (1), 2000196, 2021
222021
Room-temperature fabricated multilevel nonvolatile lead-free cesium halide memristors for reconfigurable in-memory computing
TK Su, WK Cheng, CY Chen, WC Wang, YT Chuang, GH Tan, HC Lin, ...
ACS nano 16 (8), 12979-12990, 2022
212022
Sensor-based approximate adder design for accelerating error-tolerant and deep-learning applications
NC Huang, SY Chen, KC Wu
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 692-697, 2019
122019
BTI-aware sleep transistor sizing algorithm for reliable power gating designs
KC Wu, IC Lin, YT Wang, SS Yang
IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and …, 2014
122014
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms
KC Wu, MC Lee, D Marculescu, SC Chang
Design, Automation, and Test in Europe (DATE) Conference & Exhibition, 1269-1274, 2012
122012
Re-synthesis for delay variation tolerance
SC Chang, CT Hsieh, KC Wu
Design Automation Conference (DAC), 814-819, 2004
122004
FOX-NAS: Fast, on-device and explainable neural architecture search
CH Liu, YS Han, YY Sung, Y Lee, HY Chiang, KC Wu
Proceedings of the IEEE/CVF International Conference on Computer Vision, 789-797, 2021
112021
CNN-based stochastic regression for IDDQ outlier identification
CH Yen, CT Chen, CY Wen, YY Chen, JN Lee, SY Kao, KC Wu, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
82023
Identifying good-dice-in-bad-neighborhoods using artificial neural networks
CH Yang, CH Yen, TR Wang, CT Chen, M Chern, YY Chen, JN Lee, ...
2021 IEEE 39th VLSI Test Symposium (VTS), 1-7, 2021
82021
Fault-tolerance mechanism analysis on NVDLA-based design using open neural network compiler and quantization calibrator
SM Liu, L Tang, NC Huang, DY Tsai, MX Yang, KC Wu
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-3, 2020
82020
Aging-aware chip health prediction adopting an innovative monitoring strategy
YT Wang, KC Wu, CH Chou, SC Chang
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
82019
NBTI and leakage reduction using ILP-based approach
IC Lin, KH Li, CH Lin, KC Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (9 …, 2014
82014
The 2020 low-power computer vision challenge
X Hu, MC Chang, Y Chen, R Sridhar, Z Hu, Y Xue, Z Wu, P Pi, J Shen, ...
2021 IEEE 3rd International Conference on Artificial Intelligence Circuits …, 2021
72021
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