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Abhijit Das
Abhijit Das
Post-Doctoral Researcher, UPC BarcelonaTech
Verified email at upc.edu - Homepage
Title
Cited by
Cited by
Year
SECTAR: Secure NoC using Trojan aware routing
R Manju, A Das, J Jose, P Mishra
2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2020
352020
Critical packet prioritisation by slack-aware re-routing in on-chip networks
A Das, S Babu, J Jose, S Jose, M Palesi
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018
142018
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique
RSR Raj, A Das, J Jose
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
82017
LOKI: a hardware trojan affecting multiple components of an SOC
M Rajan, A Das, J Jose
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 176-181, 2022
62022
Opportunistic caching in noc: exploring ways to reduce miss penalty
A Das, A Kumar, J Jose, M Palesi
IEEE Transactions on Computers 70 (6), 892-905, 2021
62021
Revising NoC in Future Multicore-Based Consumer Electronics for Performance
A Das, A Kumar, J Jose, M Palesi
IEEE Consumer Electronics Magazine 11 (3), 79-86, 2021
62021
Trojan aware network-on-chip routing
M Rajan, A Das, J Jose, P Mishra
Network-on-chip security and privacy, 277-307, 2021
52021
Reducing off-chip miss penalty by exploiting underutilised on-chip router buffers
A Das, A Kumar, J Jose
2020 IEEE 38th International Conference on Computer Design (ICCD), 230-238, 2020
52020
Exploiting on-chip routers to store dirty cache blocks in tiled chip multi-processors
A Das, A Kumar, J Jose, M Palesi
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 147-152, 2020
52020
An adaptive deflection router with dual injection and ejection units for mesh NoCs
J Jose, A Das
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
52018
Data criticality in multithreaded applications: An insight for many-core systems
A Das, J Jose, P Mishra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (9 …, 2021
32021
WiBS: A Modular and Scalable Wireless Infrastructure in a Cycle-Accurate NoC Simulator
M Saha, A Das, J Jose
2022 15th IEEE/ACM International Workshop on Network on Chip Architectures …, 2022
12022
Designing Data-Aware Network-on-Chip for Performance
A Das, J Jose
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 428-433, 2022
12022
Adaptive packet throttling technique for congestion management in mesh nocs
NS Aswathy, RSR Raj, A Das, J Jose, VR Josna
International Symposium on VLSI Design and Test, 337-344, 2017
12017
Technical Program Committee Chairs
A Das, MF Reza, JL Abellán, A Monemi, E Russo, GC La Delfa, M Palesi
Network on Chip Architectures (NoCArc), 2023
2023
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators
M Palesi, E Russo, A Das, J Jose
2023 IEEE International Parallel and Distributed Processing Symposium …, 2023
2023
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators
A Das, E Russo, M Palesi
arXiv preprint arXiv:2210.14657, 2022
2022
On Analyzing Free-Riding Behavior in BitTorrent Communities
A Das, A Bhattacharjee
Proceedings of the 2015 17th UKSIM-AMSS International Conference on …, 2015
2015
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)| 978-1-6654-6605-9/22/$31.00© 2022 IEEE| DOI: 10.1109/ISVLSI54635. 2022.00103
H Abunahla, T Adegbija, F Afghah, S Agarwal, S Ahlawat, QA Ahmed, ...
Technical Program Committee Chairs
P Bahrebar, J Jose, A Das, MF Reza, E Russo, GC La Delfa, M Palesi
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Articles 1–20