| Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications A Biswas, AP Chandrakasan 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 488-490, 2018 | 369 | 2018 |
| CONV-SRAM: An energy-efficient SRAM with in-memory dot-product computation for low-power convolutional neural networks A Biswas, AP Chandrakasan IEEE Journal of Solid-State Circuits 54 (1), 217-230, 2018 | 318 | 2018 |
| DC-DC converter for high granularity, sub-string MPPT in photovoltaic applications using a virtual-parallel connection S Poshtkouhi, A Biswas, O Trescases 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and …, 2012 | 78 | 2012 |
| A 28 nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency A Biswas, Y Sinangil, AP Chandrakasan IEEE Journal of Solid-State Circuits 50 (7), 1540 - 1549, 2015 | 46 | 2015 |
| A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency A Biswas, Y Sinangil, AP Chandrakasan ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), 2014 | 46 | 2014 |
| A 0.36 V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI A Biswas, AP Chandrakasan ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 433-436, 2016 | 19 | 2016 |
| Techniques for reducing parasitic loss in switched-capacitor based DC-DC converter A Biswas, M Kar, P Mandal 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and …, 2013 | 10 | 2013 |
| An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications A Biswas, H Sanghvi, M Mehendale, G Preet 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 9 | 2022 |
| Energy-efficient smart embedded memory design for IoT and AI A Biswas Massachusetts Institute of Technology, 2018 | 7 | 2018 |
| An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS A Biswas, U Arslan, F Hamzaoglu, AP Chandrakasan 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 5 | 2017 |
| Computation in-memory architecture for analog-to-digital conversion A Biswas, MM Mehendale US Patent 11,551,745, 2023 | 3 | 2023 |
| February. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for lowpower CNN-based machine learning applications. In 2018 IEEE International Solid-State … A Biswas, AP Chandrakasan IEEE, 2018 | 2 | 2018 |
| Computation in-memory using 6-transistor bit cells A Biswas, MM Mehendale, H Sanghvi US Patent App. 17/162,694, 2021 | 1 | 2021 |
| Response of nitrogen and zinc fertilization on nutrient uptake and seed quality of late sown wheat. AP Chowdhury, A Biswas, P Mandal Journal of Sylhet University of Agriculture 5, 181-188, 2018 | 1 | 2018 |
| Energy-efficient SRAM design in 28nm FDSOI Technology A Biswas Massachusetts Institute of Technology, 2014 | | 2014 |
| A 28-nm FDSOI Integrated, Reconfigurable, Switched-Capacitor Step-up DC-DC Converter with 88% Peak Efficiency A Biswas, Y Sinangil, AP Chandrakasan Circuits and Systems for Information Processing, Communications, Multimedia …, 0 | | |
Shahab PoshtkouhiUniversity of TorontoVerified email at utoronto.ca
