| Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ... 2017 international joint conference on neural networks (IJCNN), 2227-2234, 2017 | 189 | 2017 |
| A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems D Brüderle, MA Petrovici, B Vogginger, M Ehrlich, T Pfeil, S Millner, ... Biological cybernetics 104, 263-296, 2011 | 142 | 2011 |
| A biological-realtime neuromorphic system in 28 nm CMOS using low-leakage switched capacitor circuits C Mayr, J Partzsch, M Noack, S Hänzsche, S Scholze, S Höppner, ... IEEE transactions on biomedical circuits and systems 10 (1), 243-254, 2015 | 105 | 2015 |
| Live demonstration: A scaled-down version of the brainscales wafer-scale neuromorphic system J Schemmel, A Grübl, S Hartmann, A Kononov, C Mayr, K Meier, S Millner, ... 2012 IEEE international symposium on circuits and systems (ISCAS), 702-702, 2012 | 85 | 2012 |
| 10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS B Noethen, O Arnold, EP Adeva, T Seifert, E Fischer, S Kunze, E Matúš, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 57 | 2014 |
| A 32 GBit/s communication SoC for a waferscale neuromorphic system S Scholze, H Eisenreich, S Höppner, G Ellguth, S Henker, M Ander, ... Integration 45 (1), 61-75, 2012 | 55 | 2012 |
| VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality S Scholze, S Schiefer, J Partzsch, S Hartmann, CG Mayr, S Höppner, ... Frontiers in neuroscience 5, 117, 2011 | 49 | 2011 |
| Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS M Noack, J Partzsch, CG Mayr, S Hänzsche, S Scholze, S Höppner, ... Frontiers in neuroscience 9, 121030, 2015 | 47 | 2015 |
| The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing S Höppner, Y Yan, A Dixius, S Scholze, J Partzsch, M Stolba, F Kelber, ... arXiv preprint arXiv:2103.08392, 2021 | 39 | 2021 |
| A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications S Haas, T Seifert, B Nöthen, S Scholze, S Höppner, A Dixius, EP Adeva, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 37 | 2017 |
| Dynamic voltage and frequency scaling for neuromorphic many-core systems S Höppner, Y Yan, B Vogginger, A Dixius, J Partzsch, F Neumärker, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 30 | 2017 |
| Adaptive body bias aware implementation for ultra-low-voltage designs in 22FDX technology S Höppner, H Eisenreich, D Walter, A Scharfe, A Oefelein, F Schraut, ... IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2159-2163, 2019 | 29 | 2019 |
| A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates M Winter, S Kunze, EP Adeva, B Mennenga, E Matûs, G Fettweis, ... 2012 IEEE International Solid-State Circuits Conference, 216-218, 2012 | 29 | 2012 |
| Highly integrated packet-based AER communication infrastructure with 3Gevent/s throughput S Hartmann, S Schiefer, S Scholze, J Partzsch, C Mayr, S Henker, ... 2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010 | 29 | 2010 |
| Approximate fixed-point elementary function accelerator for the SpiNNaker-2 neuromorphic chip M Mikaitis, DR Lester, D Shang, S Furber, G Liu, J Garside, S Scholze, ... 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH), 37-44, 2018 | 23 | 2018 |
| Dynamic power management for neuromorphic many-core systems S Höppner, B Vogginger, Y Yan, A Dixius, S Scholze, J Partzsch, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (8), 2973-2986, 2019 | 22 | 2019 |
| Pattern representation and recognition with accelerated analog neuromorphic systems MA Petrovici, S Schmitt, J Klähn, D Stöckel, A Schroeder, G Bellec, J Bill, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 22 | 2017 |
| A 16-Channel Fully Configurable Neural SoC With 1.52 W/Ch Signal Acquisition, 2.79 W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural … SMA Zeinolabedin, FM Schüffny, R George, F Kelber, H Bauer, S Scholze, ... IEEE Transactions on Biomedical Circuits and Systems 16 (1), 94-107, 2022 | 21 | 2022 |
| An MPSoC for energy-efficient database query processing S Haas, O Arnold, B Nöthen, S Scholze, G Ellguth, A Dixius, S Höppner, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 20 | 2016 |
| Classification with deep neural networks on an accelerated analog neuromorphic system S Schmitt, J Klähn, G Bellec, A Grübl, M Güttler, A Hartel, S Hartmann, ... Proceedings of the 2017 IEEE International Joint Conference on Neural Networks, 2017 | 12 | 2017 |
