| A 4096‐neuron 1M‐synapse 3.8pJ/SOP Spiking Neural Network with On‐chip STDP Learning and Sparse Weights in 10nm FinFET CMOS GK Chen, R Kumar, HE Sumbul, P Knag, RK Krishnamurthy IEEE VLSI Circuits, 2018, 2018 | 187 | 2018 |
| Building trusted ICs using split fabrication K Vaidyanathan, BP Das, HE Sumbul, R Liu, L Pileggi Hardware-Oriented Security and Trust (HOST), 2014 | 154* | 2014 |
| A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing Q Zhu, B Akin, HE Sumbul, F Sadi, JC Hoe, L Pileggi, F Franchetti 2013 IEEE international 3D systems integration conference (3DIC), 1-7, 2013 | 147 | 2013 |
| Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware Q Zhu, T Graf, HE Sumbul, L Pileggi, F Franchetti 2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013 | 135 | 2013 |
| Efficient and Secure Intellectual Property (IP) Design with Split Fabrication K Vaidyanathan, R Liu, HE Sumbul, Q Zhu, F Franchetti, L Pileggi Hardware-Oriented Security and Trust (HOST), 2014 | 84 | 2014 |
| Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ... 27th IEEE International Symposium On Field-Programmable Custom Computing …, 2019 | 66 | 2019 |
| A 617TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS PC Knag, GK Chen, HE Sumbul, R Kumar, MA Anders, H Kaul, SK Hsu, ... 2020 Symposia on VLSI Technology and Circuits, 2020 | 49 | 2020 |
| System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars HE Sumbul, TF Wu, Y Li, SS Sarwar, W Koven, E Murphy-Trotzky, X Cai, ... IEEE Custom Integrated Circuits Conference (CICC), 2022 | 23 | 2022 |
| Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks D Przewlocka-Rus, SS Sarwar, HE Sumbul, Y Li, BD Salvo tinyML Research Symposium, 2022 | 21 | 2022 |
| Fast smith-waterman hardware implementation Z Nawaz, K Bertels, HE Sümbül 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 18 | 2010 |
| All-magnetic magnetoresistive random access memory based on four terminal mCell device DM Bromberg, HE Sumbul, JG Zhu, L Pileggi Journal of Applied Physics 117 (17), 2015 | 16 | 2015 |
| A 2.9–33.0 TOPS/W reconfigurable 1-D/2-D compute-near-memory inference accelerator in 10-nm FinFET CMOS HE Sumbul, GK Chen, PC Knag, R Kumar, MA Anders, H Kaul, SK Hsu, ... IEEE Solid-State Circuits Letters 3, 118-121, 2020 | 8 | 2020 |
| A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows L Mei, H Liu, T Wu, HE Sumbul, M Verhelst, E Beigne DATE, 2022 | 7 | 2022 |
| A synthesis methodology for application-specific logic-in-memory designs HE Sumbul, K Vaidyanathan, Q Zhu, F Franchetti, L Pileggi Proceedings of the 52Nd Annual Design Automation Conference, 1-6, 2015 | 6 | 2015 |
| Evaluating and Enhancing Intel Stratix 10 FPGAs for Persistent Real-Time AI E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ... 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2019 | 5 | 2019 |
| Bitcell wth magnetic switching elements L Pileggi, DM Bromberg, HE Sumbul US Patent 9,524,767, 2016 | 5 | 2016 |
| DRESS: Dynamic REal-time Sparse Subnets Z Qu, SS Sarwar, X Dong, Y Li, E Sumbul, BD Salvo Efficient Deep Learning for Computer Vision (ECV) CVPR Workshop 2022, 2022 | 3 | 2022 |
| Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS S Hsu, A Agarwal, S Realov, M Anders, G Chen, M Kar, R Kumar, ... 2020 Symposia on VLSI Technology and Circuits, 2020 | 3 | 2020 |
| A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications M Kar, A Agarwal, S Hsu, D Moloney, G Chen, R Kumar, H Sumbul, ... 2020 Symposia on VLSI Technology and Circuits, 2020 | 3 | 2020 |
| Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range MA Anders, H Kaul, S Kim, GK Chen, R Kumar, HE Sumbul, PC Knag, ... International Solid-State Circuits Conference, 2020 | 3* | 2020 |
Lawrence PileggiCoraluppi Head and Tanoto Professor of ECE, Carnegie Mellon UniversityVerified email at andrew.cmu.edu
