| Radix-2 multioperand and multiformat streaming online addition J Villalba, T Lang, J Hormigo IEEE Transactions on Computers 61 (6), 790-803, 2011 | 17 | 2011 |
| CIBERER: Spanish national network for research on rare diseases: A highly productive collaborative initiative J Luque, I Mendes, B Gómez, B Morte, M López de Heredia, E Herreras, ... Clinical Genetics 101 (5-6), 481-493, 2022 | 9 | 2022 |
| Fast HUB floating-point adder for FPGA J Villalba, J Hormigo, S González-Navarro IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 1028-1032, 2018 | 9 | 2018 |
| Redundant floating-point decimal CORDIC algorithm A Vazquez, J Villalba-Moreno, E Antelo, EL Zapata IEEE Transactions on Computers 61 (11), 1551-1562, 2011 | 9 | 2011 |
| Unbiased rounding for HUB floating-point addition J Villalba-Moreno, J Hormigo, S González-Navarro IEEE Transactions on Computers 67 (9), 1359-1365, 2018 | 8 | 2018 |
| Digit recurrence floating-point division under HUB format J Villalba-Moreno 2016 IEEE 23nd symposium on computer arithmetic (ARITH), 79-86, 2016 | 8 | 2016 |
| On-line decimal adder with RBCD representation CG Vega, SG Navarro, JV Moreno, EL Zapata 2012 IEEE 23rd International Conference on Application-Specific Systems …, 2012 | 5 | 2012 |
| Water quality assessment in a Caribbean saltwater wetland R Perez, F Riveiro, M Jimenez-Nod, L Mangianello, C Vega, R Cova, ... Revista Ingeniería UC 24 (3), 417-427, 2017 | 3 | 2017 |
| Evaluación de la calidad y el caudal de aguas de una subcuenca hidrográfica ubicada en un parque nacional E Balza, M Zapata, M Jiménez-Noda, L Manganiello, C Vega, R Cova, ... Revista INGENIERÍA UC 26 (1), 105-118, 2019 | 1 | 2019 |
| Floating Point Square Root under HUB Format J Villalba-Moreno, J Hormigo 2017 IEEE International Conference on Computer Design (ICCD), 447-454, 2017 | 1 | 2017 |
| Proceedings of IEEE 22nd Symposium on Computer Arithmetic JM Muller, A Tisserand, JV Moreno IEEE, 2015 | 1 | 2015 |
| Floating Point HUB Adder for RISC-V Sargantana Processor G Bandera-Burgueño, J Salamero, M Moreto, J Villalba-Moreno Cornell University, 2023 | | 2023 |
| High-radix formats for enhancing floating-point FPGA implementations J Villalba-Moreno, J Hormigo-Aguilar Springer, 2022 | | 2022 |
| Floating–Point Fused Multiply–Add under HUB Format J Hormigo, J Villalba-Moreno, S Gonzalez-Navarro 2020 IEEE 27th Symposium on Computer Arithmetic (ARITH), 1-8, 2020 | | 2020 |
| Reproducible Summation under HUB Format J Villalba-Moreno, J Hormigo, F Jaime 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH), 38-45, 2019 | | 2019 |
| Introduction to the Special Issue on Computer Arithmetic J Hormigo, JM Muller, S Oberman, N Revol, A Tisserand, ... IEEE Transactions on Computers 66 (12), 1991-1993, 2017 | | 2017 |
| Digit recurence division under HUB format J Villalba-Moreno | | 2016 |
| Decimal Multiformat Online Addition C Garcia-Vega, S Gonzalez-Navarro, P Balboa-La Chica, ... IEEE Transactions on Computers 65 (10), 3203-3209, 2016 | | 2016 |
| Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest J Hormigo-Aguilar, J Villalba-Moreno IEEE, 2016 | | 2016 |
| New formats for computing with real-numbers under round-to-nearest J Hormigo-Aguilar, J Villalba-Moreno | | 2015 |
