| Spectral shaping of circuit errors in digital-to-analog converters I Galton IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997 | 417 | 1997 |
| A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation S Pamarti, L Jansson, I Galton IEEE Journal of Solid-State Circuits 39 (1), 49-62, 2004 | 339 | 2004 |
| A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC E Siragusa, I Galton Solid-State Circuits, IEEE Journal of 39 (12), 2126-2138, 2004 | 284 | 2004 |
| A mostly-digital variable-rate continuous-time delta-sigma modulator ADC G Taylor, I Galton IEEE Journal of Solid-State Circuits 45 (12), 2634-2646, 2010 | 276 | 2010 |
| A multiple-crystal interface PLL with VCO realignment to reduce phase noise S Ye, L Jansson, I Galton IEEE Journal of Solid-State Circuits 37 (12), 1795-1803, 2002 | 246 | 2002 |
| Digital cancellation of D/A converter noise in pipelined A/D converters I Galton IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000 | 217 | 2000 |
| Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL KJ Wang, A Swaminathan, I Galton IEEE Journal of Solid-State Circuits 43 (12), 2787-2797, 2008 | 213 | 2008 |
| Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL KJ Wang, A Swaminathan, I Galton IEEE Journal of Solid-State Circuits 43 (12), 2787-2797, 2008 | 213 | 2008 |
| Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL KJ Wang, A Swaminathan, I Galton IEEE Journal of Solid-State Circuits 43 (12), 2787-2797, 2008 | 213 | 2008 |
| Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL KJ Wang, A Swaminathan, I Galton Solid-State Circuits, IEEE Journal of 43 (12), 2787-2797, 2008 | 213 | 2008 |
| Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL KJ Wang, A Swaminathan, I Galton IEEE International Solid-State Circuits Conference, 342-343, 618, 2008 | 213 | 2008 |
| A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction A Panigada, I Galton IEEE Journal of Solid-State Circuits 44 (12), 3314-3328, 2009 | 195 | 2009 |
| A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction A Panigada, I Galton IEEE Journal of Solid-State Circuits 44 (12), 3314-3328, 2009 | 195 | 2009 |
| A Wide-Bandwidth 2.4 GHz ISM Band Fractional- PLL With Adaptive Phase Noise Cancellation A Swaminathan, KJ Wang, I Galton IEEE Journal of Solid-State Circuits 42 (12), 2639-2650, 2007 | 171 | 2007 |
| Delta-sigma data conversion in wireless transceivers I Galton IEEE Transactions on Microwave Theory and Techniques 50 (1), 302-315, 2002 | 170 | 2002 |
| Delta-sigma modulator based A/D conversion without oversampling I Galton, HT Jensen IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1995 | 168 | 1995 |
| Synergistic design of DSP and power amplifiers for wireless communications PM Asbeck, LE Larson, IG Galton IEEE Transactions on Microwave Theory and Techniques 49 (11), 2163-2169, 2001 | 146 | 2001 |
| Combined angle demodulator and digitizer I Galton US Patent 5,369,404, 1994 | 146 | 1994 |
| Digital background correction of harmonic distortion in pipelined ADCs A Panigada, I Galton IEEE Transactions on Circuits and Systems I: Regular Papers 53 (9), 1885-1895, 2006 | 138 | 2006 |
| A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB G Taylor, I Galton Solid-State Circuits, IEEE Journal of 48 (4), 983-995, 2013 | 137 | 2013 |
