| An integrated single-shot spectrometer with large bandwidth-resolution ratio and wide operation temperature range A Li, C Wang, F Bao, W Fang, Y Liang, R Cheng, S Pan PhotoniX 4 (1), 29, 2023 | 16 | 2023 |
| Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution S Liu, W Fang, Y Lu, Q Zhang, H Zhang, Z Xie arXiv preprint arXiv:2312.08617, 2023 | 8 | 2023 |
| Specllm: Exploring generation and review of vlsi design specification with large language model M Li, W Fang, Q Zhang, Z Xie arXiv preprint arXiv:2401.13266, 2024 | 3 | 2024 |
| MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design W Fang, Y Lu, S Liu, Q Zhang, C Xu, LW Wills, H Zhang, Z Xie 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs W Fang, M Li, M Li, Z Yan, S Liu, H Zhang, Z Xie arXiv preprint arXiv:2402.00386, 2024 | 2 | 2024 |
| r-map: Relating implementation and specification in hardware refinement checking W Fang, G Hu, H Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 1 | 2023 |
| WASIM: A word-level abstract symbolic simulation framework for hardware formal verification W Fang, H Zhang International Conference on Tools and Algorithms for the Construction and …, 2023 | 1 | 2023 |
| Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization W Fang, S Liu, H Zhang, Z Xie arXiv preprint arXiv:2403.18453, 2024 | | 2024 |
| The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models L Chen, Y Chen, Z Chu, W Fang, TY Ho, Y Huang, S Khan, M Li, X Li, ... arXiv preprint arXiv:2403.07257, 2024 | | 2024 |
Zhiyao XieAssistant Professor, Hong Kong University of Science and Technology在 ust.hk 的电子邮件经过验证
