| LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS A Boni, A Pierazzi, D Vecchi IEEE Journal of Solid-State Circuits 36 (4), 706-711, 2001 | 313 | 2001 |
| An 800 MS/s dual-residue pipeline ADC in 40 nm CMOS D Vecchi, J Mulder, FML van der Goes, JR Westra, E Ayranci, CM Ward, ... IEEE journal of solid-state circuits 46 (12), 2834-2844, 2011 | 36 | 2011 |
| An 800MS/s dual-residue pipeline ADC in 40nm CMOS J Mulder, FML van der Goes, D Vecchi, JR Westra, E Ayranci, CM Ward, ... 2011 IEEE International Solid-State Circuits Conference, 184-186, 2011 | 27 | 2011 |
| A 6-bit, 1.2 GHz Interleaved SAR ADC in 90nm CMOS S Dondi, D Vecchi, A Boni, M Bigi 2006 Ph. D. Research in Microelectronics and Electronics, 301-304, 2006 | 21 | 2006 |
| Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS A Boni, M Parenti, D Vecchi IEEE Transactions on Circuits and Systems II: Express Briefs 53 (6), 429-433, 2006 | 20 | 2006 |
| 26.3 An 800MS/s 10b/13b receiver for 10GBASE-T ethernet in 28nm CMOS J Mulder, D Vecchi, Y Ke, S Bozzola, M Core, N Saputra, Q Zhang, J Riley, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 16 | 2015 |
| Systematic design and modelling of high-resolution, high-speed pipeline ADCs M Parenti, D Vecchi, A Boni, G Chiorboli Measurement 37 (4), 344-351, 2005 | 16 | 2005 |
| 100-MS/s 14-b track-and-hold amplifier in 0.18-/spl mu/m CMOS D Vecchi, C Azzolini, A Boni, F Chaahoub, L Crespi Proceedings of the 31st European Solid-State Circuits Conference, 2005 …, 2005 | 11 | 2005 |
| 8.5 A sub-1.75 W full-duplex 10GBASE-T transceiver in 40nm CMOS JR Westra, J Mulder, Y Ke, D Vecchi, X Liu, E Arslan, J Wan, Q Zhang, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 7 | 2014 |
| Design of a 2-GS/s 8-b self-calibrating ADC in 0.18/spl mu/m CMOS technology C Azzolini, A Boni, A Facen, M Parenti, D Vecchi 2005 IEEE International Symposium on Circuits and Systems, 1386-1389, 2005 | 7 | 2005 |
| Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers JR Westra, J Mulder, Y Ke, D Vecchi, X Liu, E Arslan, J Wan, Q Zhang, ... Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-8, 2014 | 6 | 2014 |
| LVDS I/O for Gb/s-per-Pin Operation in 0.35-um CMOS A Boni, A Pierazzi, D Vecchi IEEE Journal of Solid State Circuits 36 (4), 2001 | 5 | 2001 |
| High-level accurate model of high-resolution pipelined ADC's C Azzolini, D Vecchi, A Boni, G Chiorboli 2006 IEEE Instrumentation and Measurement Technology Conference Proceedings …, 2006 | 4 | 2006 |
| A 750 mW class G ADSL line driver with offset-controlled amplifier hand-over D Vecchi, C Morandi Southwest Symposium on Mixed-Signal Design, 2003., 253-258, 2003 | 4 | 2003 |
| Modeling and design optimisation for high-resolution, high-speed pipeline ADC’s M Parenti, D Vecchi, A Boni, G Chiorboli Measurement 37, 2005 | 3 | 2005 |
| A Low-Distortion CLASS G Line Driver for central-office ADSL modem ID Vecchi, A Boni, C Morandi Analog Integrated Circuits and Signal Processing 34, 59-69, 2003 | 3 | 2003 |
| Exploiting SiGe BiCMOS technology in the design of A12-B 200-MS/S pipeline ADC C Azzolini, A Boni, P Milanesi, D Vecchi IET Digital Library, 2005 | 2 | 2005 |
| Design of a 14-bit, 100-MS/s, pipelined analog-to-digital convertor in 0.18-μm CMOS technology D Vecchi, C Azzolini, A Boni, F Chaahoub, L Crespi IET Digital Library, 2005 | 2 | 2005 |
| DAC calibration by weighting capacitor rotation in a pipelined ADC. G Chiorboli, S Dondi, C Morandi, D Vecchi Circuits, Signals, and Systems, 31-35, 2005 | 2 | 2005 |
| Overvoltage protection circuit with digital control JR Westra, J Mulder, Q Zhang, JA Riley, D Vecchi US Patent 9,543,752, 2017 | 1 | 2017 |
