| A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ... IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021 | 33 | 2021 |
| Low cost flex powered gesture detection system and its applications P Telluri, S Manam, S Somarouthu, JM Oli, C Ramesh 2020 Second International Conference on Inventive Research in Computing …, 2020 | 14 | 2020 |
| Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs R Chinthala, NS Murty 2019 International Conference on Computer Communication and Informatics …, 2019 | 6 | 2019 |
| An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique N Soni, R Chinthala 2020 International Conference on Smart Electronics and Communication (ICOSEC …, 2020 | 3 | 2020 |
| Implementation of an area efficient high throughput architecture for sparse matrix LU factorization GP Kumar, C Ramesh 2019 3rd International Conference on Electronics, Materials Engineering …, 2019 | 3 | 2019 |
| An efficient design methodology to speed up the FPGA implementation of artificial neural networks KV Vineetha, MMSK Reddy, C Ramesh, DG Kurup Engineering Science and Technology, an International Journal 47, 101542, 2023 | 2 | 2023 |
| Implementation of Neural Network Based Digital Pre-distorter for Power Amplifier Linearisation MA Bharadwaj, C Ramesh, RVS Devi 2024 Second International Conference on Emerging Trends in Information …, 2024 | | 2024 |
| Cost Efficient Location Tracking and Health Monitoring System for Soldier Safety R Jayaramu, GSK Reddy, R Chinthala, TL Purushottama, ... 2023 Global Conference on Information Technologies and Communications (GCITC …, 2023 | | 2023 |
| FPGA Implementation of UaL Decomposition, an alternative to the LU factorization S Ruchitha, R Chinthala Mathematical Statistician and Engineering Applications 71 (4), 1081-1094, 2022 | | 2022 |
| Complex Binary Number System-based Co-Processor Design for Signal Processing Applications SS Santosh, TS Swaroop, T Kavya, R Chinthala 2021 5th International Conference on Electronics, Materials Engineering …, 2021 | | 2021 |
| High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF (4) CC Kumar, R Chinthala 2020 4th International Conference on Electronics, Materials Engineering …, 2020 | | 2020 |
| Sensor Data Acquisition and De-noising using FPGA K Harikrishnan, HN Vishwas, KV Vineetha, R Chinthala International Journal of Scientific & Engineering Research 11 (8), 1673 - 1680, 2020 | | 2020 |
| Implementation of Blind Source Separation using FPGA CP Anu Vyshakh, KV Vineetha, R Chinthala International Journal of Scientific & Engineering Research 11 (9), 1098 - 1104, 2020 | | 2020 |
| Hardware-Software Co-Design Accelerators for Sparse BLAS C Ramesh | | 2019 |
| Exploration of Cache Line Size for Sawtooth Compressed Row Storage based SpMV Multiplication R Chinthala, A Datta, SK Nandy 13th Australasian Symposium on Parallel and Distributed Computing, 93-96, 2015 | | 2015 |
Vitor SilvaProfessor de Engenharia Electrotécnica e de Computadores, Universidade de CoimbraVerified email at co.it.pt
