| Intelligent gate drive for fast switching and crosstalk suppression of SiC devices Z Zhang, J Dix, FF Wang, BJ Blalock, D Costinett, LM Tolbert IEEE Transactions on Power Electronics 32 (12), 9319-9332, 2017 | 128 | 2017 |
| CMOS gate drive IC with embedded cross talk suppression circuitry for SiC devices J Dix, Z Zhang, BJ Blalock 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 684-691, 2016 | 10 | 2016 |
| Programmable energy-efficient analog multilayer perceptron architecture suitable for future expansion to hardware accelerators J Dix, J Holleman, BJ Blalock Journal of Low Power Electronics and Applications 13 (3), 47, 2023 | 2 | 2023 |
| Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI Naveed, J Dix Journal of Low Power Electronics and Applications 13 (4), 64, 2023 | 1 | 2023 |
| A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS JS Venker, L Vincent, J Dix Journal of Low Power Electronics and Applications 13 (4), 55, 2023 | 1 | 2023 |
| A Resistor-less, Nano-Watt CMOS Voltage Reference with High PSRR J Dix 2021 22nd International Symposium on Quality Electronic Design (ISQED), 19-23, 2021 | 1 | 2021 |
| Comparison of Two RF Rectifiers Designed in FDSOI 22nm for RF Energy Harvesting J Dix 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 313-316, 2022 | | 2022 |
| 65nm Fast Response Radiation Hardened by Design Analog Comparator L Vincent, T Langdon, J Dix GOMAC, 2021 | | 2021 |
| Radiation Hardened Fully Differential Amplifier with 4.6 GHz Gain-Bandwidth Product T Langdon, L Vincent, J Dix GOMAC, 2021 | | 2021 |
| Analog Spiking Neural Network Implementing Spike Timing-Dependent Plasticity on 65 nm CMOS L Vincent University of Arkansas, 2021 | | 2021 |
| Configurable Low Power Analog Multilayer Perceptron JM Dix | | 2018 |
| CMOS Gate Drive IC With Embedded Cross Talk Suppression Circuitry For Power Electronic Applications JM Dix | | 2015 |
Benjamin BlalockThe University of TennesseeVerified email at utk.edu
