| Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load AK Dubey, RK Nagaria Microelectronics Journal 78 (August 2018), 1-10, 2018 | 42 | 2018 |
| Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage AK Dubey, RK Nagaria Analog Integrated Circuits and Signal Processing, 1-11, 2019 | 26 | 2019 |
| Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 27 (13), 1850204, 2018 | 19 | 2018 |
| Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure R Jain, AK Dubey, V Varshney, RK Nagaria 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical …, 2017 | 17 | 2017 |
| Voltage comparison based high speed & low power domino circuit for wide fan-in gates PK Pal, AK Dubey, SR Kassa, RK Nagaria 2016 IEEE International Conference on Electron Devices and Solid-State …, 2016 | 11 | 2016 |
| Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 9th Annual Information Technology, Electromechanical Engineering and …, 2019 | 10 | 2019 |
| Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process V Varshney, AK Dubey, A Kumar, PK Pal, RK Nagaria 2018 3rd International Innovative Applications of Computational Intelligence …, 2018 | 10 | 2018 |
| Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 28 (09), 1950157, 2019 | 7 | 2019 |
| Enhanced slew rate, constant-gmrail-to-rail OpAmp using 1:2 current mirror biasing technique AK Dubey, RK Nagaria, PK Pal, RK Singh 2016 International Conference on Computing, Communication and Automation …, 2016 | 7 | 2016 |
| Efficient technique to reduce power dissipation of Op-Amps at high speed AK Dubey, P Srivastava, M Pattanaik 2015 International Conference on Robotics, Automation, Control and Embedded …, 2015 | 7 | 2015 |
| Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 IEEE Conference on Information and Communication Technology, 1-4, 2019 | 4 | 2019 |
| Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit A Kumar, PK Pal, V Varshney, AK Dubey, RK Nagaria Advances in VLSI, Communication, and Signal Processing, 631-642, 2021 | 3 | 2021 |
| An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic KK Mishra, AK Dubey, V Varshney, KP Pandey 2020 IEEE Students Conference on Engineering & Systems (SCES), 1-6, 2020 | 3 | 2020 |
| Design and performance of high-speed energy-efficient CMOS double tail dynamic latch comparator using GACOBA load suitable for low voltage Applications V Varshney, AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 30 (11), 2150191, 2021 | 2 | 2021 |
| Low Power, Accurate Variable Gain Amplifier (VGA) with High dB-Linear Gain at 900 MHz AK Dubey, P Srivastava, M Pattanaik International Journal on Advance Research in Electrical and Electronics …, 2015 | 2 | 2015 |
| Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria Advances in VLSI, Communication, and Signal Processing, 75-87, 2021 | 1 | 2021 |
| A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications V Varshney, A Kumar, AK Dubey, P Singh, RK Nagaria 2019 International Conference on Electrical, Electronics and Computer …, 2019 | 1 | 2019 |
| A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate Ankur Kumar, Pratosh Kumar Pal, Avaneesh Kumar Dubey, Vikrant Varshney, R K ... 2018 15th IEEE India Council International Conference (INDICON) - Circuits …, 2018 | 1* | 2018 |
| A 0.18 µm β-Ga2O3 MOSFET Using Al2O3/HfO2/SiO2 Gate Dielectric for Low-VTH High-Power Electronics Applications PK Pal, AK Dubey, RK Chauhan, RK Nagaria Recent Trends in Electronics and Communication, 1009-1016, 2022 | | 2022 |
| Low-Power Enhanced Speed Two-Tail Dynamically Controlled Comparator Suitable for Subthreshold CMOS Circuits AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria Recent Trends in Electronics and Communication, 1121-1135, 2022 | | 2022 |
Dr. Vikrant VarshneySenior Application Engineer, Synopsys India Pvt LtdVerified email at synopsys.com
