Follow
Christos Georgiou
Christos Georgiou
Retired
No verified email
Title
Cited by
Cited by
Year
Blue Gene: A vision for protein science using a petaflop supercomputer
F Allen, G Almasi, W Andreoni, D Beece, BJ Berne, A Bright, J Brunheroto, ...
IBM systems journal 40 (2), 310-327, 2001
3522001
Pipelined packet processing
RM Bunce, CJ Georgiou, V Salapura
US Patent 6,836,808, 2004
2632004
Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit
CJ Georgiou, ES Kirkpatrick, TA Larsen
US Patent 6,047,248, 2000
1882000
Single chip protocol converter
C Georgiou, V Gregurick, I Nair, V Salapura
US Patent App. 10/768,828, 2005
1662005
Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit
CJ Georgiou, ES Kirkpatrick, TA Larsen
US Patent 5,940,785, 1999
1661999
Packet preprocessing interface for multiprocessor network handler
V Salapura, CJ Georgiou
US Patent 6,904,040, 2005
1212005
Fault-tolerant array of cross-point switching matrices
CJ Georgiou
US Patent 4,605,928, 1986
991986
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
CJ Georgiou, VL Gregurick, V Salapura
US Patent 7,353,362, 2008
942008
Disk drive power management system and method
CJ Georgiou, ES Kirkpatrick
US Patent 5,774,292, 1998
891998
Distributed arbitration for multiple processors
CJ Georgiou, AP Ravn
US Patent 4,633,394, 1986
891986
Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
CJ Georgiou, VL Gregurick, I Nair, V Salapura
US Patent 7,412,588, 2008
872008
High-speed switching system with flexible protocol capability
AM Varma, CJ Georgiou
US Patent 4,929,939, 1990
841990
Dynamic reallocation of data stored in buffers based on packet size
CJ Georgiou, V Salapura
US Patent 7,003,597, 2006
832006
Programmable network protocol handler architecture
CJ Georgiou, MM Denneau, V Salapura, RM Bunce
US Patent 7,072,970, 2006
81*2006
Digital phase alignment and integrated multichannel transceiver employing same
CJ Georgiou, TA Larsen, KW Lee
US Patent 5,668,830, 1997
801997
Method and system of efficient packet reordering
CJ Georgiou, V Salapura
US Patent 7,477,644, 2009
732009
Method and system for buffer occupancy reduction in packet switch network
RA Cieslak, CJ Georgiou, CS Li
US Patent 5,402,416, 1995
721995
Variable chip-clocking mechanism
CJ Georgiou, TA Larsen, E Schenfeld
US Patent 5,189,314, 1993
721993
Memory unit backup using checksum
Y Dishon, CJ Georgiou
US Patent 4,849,978, 1989
691989
Method and System for Hosting an In-Store Electronic Auction
CJ Georgiou, BE Rogowitz, M Flickner
US Patent App. 11/967,554, 2009
662009
The system can't perform the operation now. Try again later.
Articles 1–20