| Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ... ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023 | 22 | 2023 |
| An academic risc-v silicon implementation based on open-source components J Abella, C Bulla, G Cabo, FJ Cazorla, A Cristal, M Doblas, R Figueras, ... 2020 XXXV conference on design of circuits and integrated systems (DCIS), 1-6, 2020 | 21 | 2020 |
| DVINO: A RISC-V vector processor implemented in 65nm technology G Cabo, G Candón, X Carril, M Doblas, M Domínguez, A González, ... 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 1-6, 2022 | 6 | 2022 |
| eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem L Alvarez, A Ruiz, A Bigas-Soldevilla, P Kuroedov, A Gonzalez, H Mahale, ... Proceedings of the 20th ACM International Conference on Computing Frontiers …, 2023 | | 2023 |
| Design of a Load/Store Queue with Out-of-Order Execution AJ Ruíz Ramírez Universitat Politècnica de Catalunya, 2016 | | 2016 |
