| Design and synthesis of combinational circuits using reversible decoder in Xilinx GC Naguboina, K Anusudha 2017 International Conference on Computer, Communication and Signal …, 2017 | 25 | 2017 |
| Design and implementation of programmable read only memory using reversible decoder on FPGA GC Naguboina, K Anusudha 2017 Fourth International Conference on Signal Processing, Communication and …, 2017 | 6 | 2017 |
| Anusudha. k “Design and Synthesis of Combinational Circuits using Reversible decoder in Xilinx” International Conference on Computer Communication and Signal Processing GC Naguboina ICCCSP-17, Chennai, 0 | 5 | |
| Realization and synthesis of ring counter and twisted ring counter using reversible logical computation with minimum quantum cost GC Naguboina, K Anusudha 2018 International Conference on Inventive Research in Computing …, 2018 | 4 | 2018 |
| Design and Implementation of BCD to Seven Segment Display Decoder using reversible decoder on FPGA GC Naguboina, K Anusudha International Journal of Computing and Applications 13 (2), 265-275, 2018 | 4 | 2018 |
| Design and implementation of PAL and PLA using reversible logic on FPGA SPARTAN 3E K Anusudha, GC Naguboina 2017 Fourth International Conference on Signal Processing, Communication and …, 2017 | 3 | 2017 |
| Implementation of MAC unit Modified IEEE-754 Floating Point Multiplier with Enhanced Speed CS 1Gopi Chand Naguboina, G. Prasanna Sravya, B. Mohini Mukt Shabd Journal 9 (VI), 3304, 2020 | | 2020 |
| A Comparative Analysis Report on Modified Reversible Sequential Circuits Realized with Improved Quantum Cost TS Gopi Chand Naguboina i – manager’s Journal on Circuits and Systems 7 (1), 2019 | | 2019 |
| Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL GC Naguboina, T Sravya i-Manager's Journal on Digital Signal Processing 7 (1), 20, 2019 | | 2019 |
| A Comparative Analysis Report on Modified Reversible Sequential Circuits realized with Improved Quantum cost GC Naguboina, T Sravya I-Manager's Journal on Circuits & Systems 7 (1), 2018 | | 2018 |
| Result Analysis of Modified Sequential Circuits Realized Using Reversible Logical Computation With Improved Quantum Cost in Comparison With Irreversible Sequential Circuits GC Naguboina Available at SSRN 3281503, 2018 | | 2018 |
| Realization and Synthesis of Modified Synchronous and Asynchronous Counters using Reversible Logical Computation with Improved Quantum Cost TS Gopi Chand Naguboina, K. Anusudha, International Conference on New Trends in Engineering and Technology (ICNTET …, 2018 | | 2018 |
| Realization and Synthesis of 4 – bit Universal Shift Register using Logical Reversible Computation in Xilinx TS Gopi Chand Naguboina, K. Anusudha, International Journal of Engineering and Technology(UAE) 7 (3.29), 769, 2018 | | 2018 |
| Realization and Synthesis of Shift Registers and Shift Counters using Reversible Logical Computation GC Naguboina, K Anusudha i-Manager's Journal on Circuits & Systems 6 (2), 22, 2017 | | 2017 |
| Realization and Synthesis of Modified Synchronous and Asynchronous Counters using Reversible Logical Computation with Improved Quantum Cost GC Naguboina, K Anusudha, T Sravya | | |
