| An fpga architecture supporting dynamically controlled power gating AAM Bsoul, SJE Wilton Field-Programmable Technology (FPT), 2010 International Conference on, 1-8, 2010 | 65 | 2010 |
| Reliability-and process variation-aware placement for FPGAs AAM Bsoul, N Manjikian, L Shang 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 42 | 2010 |
| An FPGA architecture and CAD flow supporting dynamically controlled power gating AAM Bsoul, SJE Wilton, KH Tsoi, W Luk IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 178-191, 2015 | 22 | 2015 |
| An FPGA with power-gated switch blocks AAM Bsoul, SJE Wilton 2012 International Conference on Field-Programmable Technology, 87-94, 2012 | 20 | 2012 |
| A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs AAM Bsoul, SJE Wilton Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 11 | 2012 |
| High-level synthesis-based design methodology for dynamic power-gated FPGAs R Ahmed, AAM Bsoul, SJE Wilton, P Hallschmid, R Klukas 2014 24th International Conference on Field Programmable Logic and …, 2014 | 7 | 2014 |
| Implementation of an FPGA-based low-power video processing module for a head-mounted display system AAM Bsoul, R Hoskinson, M Ivanov, S Mirabbasi, H Abdollahi 2013 IEEE International Conference on Consumer Electronics (ICCE), 214-217, 2013 | 6 | 2013 |
| A configurable architecture to limit inrush current in power-gated reconfigurable devices AAM Bsoul, SJE Wilton Journal of Low Power Electronics 10 (1), 1-15, 2014 | 4 | 2014 |
| Reliability-and Variation-Aware Placement for Field-Programmable Gate Arrays A Bsoul Queen's University, 2009 | 4 | 2009 |
| FPGA architectures and CAD algorithms with dynamic power gating support AAM Bsoul University of British Columbia, 2014 | | 2014 |
| Runtime-Controlled Energy Reduction Techniques for FPGAs AAM Bsoul, S Dueck, SJE Wilton Green Communications: Theoretical Fundamentals, Algorithms and Applications, 2012 | | 2012 |
| A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter. S Abdel-Hafeez, A Bsoul, A Shatnawi, A Gordon-Ross, S Harb Informatica (03505596) 35 (2), 2011 | | 2011 |
| Additional Reviewers FCCM 2014 A Agne, R Ahmed, J Ambrose, J Anwer, S Bayliss, T Becker, ... | | |
Steve WiltonElectrical and Computer Engineering, University of British Columbia, V6T 1Z4Verified email at ece.ubc.ca
