| A skew-free 10 GS/s 6 bit CMOS ADC with compact time-domain signal folding and inherent DEM S Zhu, B Xu, B Wu, K Soppimath, Y Chiu IEEE Journal of Solid-State Circuits 51 (8), 1785-1796, 2016 | 70 | 2016 |
| A 2-GS/s 8-bit non-interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS S Zhu, B Wu, Y Cai, Y Chiu IEEE Journal of Solid-State Circuits 53 (4), 1172-1183, 2017 | 58 | 2017 |
| A 24.7 mW 65 nm CMOS SAR-Assisted CT Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR B Wu, S Zhu, B Xu, Y Chiu IEEE Journal of Solid-State Circuits 51 (12), 2893-2905, 2016 | 44 | 2016 |
| A 40 nm CMOS derivative-free IF active-RC BPF with programmable bandwidth and center frequency achieving over 30 dBm IIP3 B Wu, Y Chiu IEEE Journal of Solid-State Circuits 50 (8), 1772-1784, 2015 | 43 | 2015 |
| 15.1 A 24.7 mW 45MHz-BW 75.3 dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS B Wu, S Zhu, B Xu, Y Chiu 2016 IEEE International Solid-State Circuits Conference (ISSCC), 270-271, 2016 | 30 | 2016 |
| A 9-bit 215 MS/s folding-flash time-to-digital converter based on redundant remainder number system in 45-nm CMOS B Wu, S Zhu, Y Zhou, Y Chiu IEEE Journal of Solid-State Circuits 53 (3), 839-849, 2018 | 26 | 2018 |
| A 2GS/s Flash ADC based on remainder number system in 65nm CMOS S Zhu, B Wu, C Yongda, Y Chiu VLSI Circuits (VLSI-Circuits), 2017 IEEE Symposium on, 2017 | 21 | 2017 |
| A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM S Zhu, B Xu, B Wu, K Soppimath, Y Chiu 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 17 | 2015 |
| A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system B Wu, S Zhu, Y Zhou, Y Chiu Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 12 | 2014 |
| An 182mW 1-60Gb/s configurable PAM-4/NRZ transceiver for large scale ASIC integration in 7nm FinFET technology N Kocaman, U Singh, B Raghavan, A Lyer, K Thasari, S Surana, JW Jung, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 120-122, 2022 | 10 | 2022 |
| Hybrid second-order noise coupling technique for continuous-time delta-sigma modulators Y Chiu, B Wu US Patent App. 15/884,018, 2018 | 8 | 2018 |
| Implicit feed-forward compensated op-amp with split pairs Y Chiu, B Wu US Patent 9,577,593, 2017 | 3 | 2017 |
| Adaptive phase alignment scheme for High-speed DACs B Wu, R Loh, L Lee, D Liu US Patent App. 62/884,123, 2019 | | 2019 |
| High-efficiency and wide-bandwidth continuous-time band-pass filters and delta-sigma converters B Wu The University of Texas at Dallas, 2016 | | 2016 |
| An 85–225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS B Wu, Y Chiu Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | | 2014 |
| Highly Linear LNA Design for Base Station Applications B Wu Delft University of Technology, 2010 | | 2010 |
Yun ChiuUT DallasVerified email at ieee.org
