| Fast Lagrangian relaxation based gate sizing using multi-threading A Sharma, D Chinnery, S Bhardwaj, C Chu 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 426-433, 2015 | 20 | 2015 |
| Fast Lagrangian relaxation-based multithreaded gate sizing using simple timing calibrations A Sharma, D Chinnery, T Reimann, S Bhardwaj, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 19 | 2019 |
| Rapid gate sizing with fewer iterations of Lagrangian Relaxation A Sharma, D Chinnery, S Dhamdhere, C Chu 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 337-343, 2017 | 13 | 2017 |
| Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling-A Fast and Effective Approach A Sharma, D Chinnery, C Chu Proceedings of the 2019 International Symposium on Physical Design, 129-137, 2019 | 9 | 2019 |
| Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware A Sharma, J Sloan, LF Wanner, SH Elmalaki, MB Srivastava, P Gupta 2013 IEEE 31st International Conference on Computer Design (ICCD), 435-438, 2013 | 8 | 2013 |
| Integrating LR Gate Sizing in an Industrial Place-and-Route Flow D Chinnery, A Sharma Proceedings of the 2022 International Symposium on Physical Design, 39-48, 2022 | 4 | 2022 |
| Gate sizing and Vth assignment for asynchronous circuits using Lagrangian relaxation G Wu, A Sharma, C Chu 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 4 | 2015 |
| Understanding software application behaviour in presence of permanent and intermittent hardware faults A Sharma University of California, Los Angeles, 2013 | 3 | 2013 |
| Lagrangian relaxation-based multi-threaded discrete gate sizer A Sharma Iowa State University, 2018 | | 2018 |
David ChinnerySiemens EDAVerified email at mentor.com
