A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL MK Hati, TK Bhattacharyya Microelectronics Journal 44 (8), 649-657, 2013 | 29 | 2013 |
Design of a low power, high speed complementary input folded regulated cascode OTA for a parallel pipeline ADC MK Hati, TK Bhattacharyya 2011 IEEE Computer Society Annual Symposium on VLSI, 114-119, 2011 | 19 | 2011 |
A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13-µm CMOS MK Hati, TK Bhattacharyya 2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015 | 18 | 2015 |
Design of low power parallel pipeline ADC in 180nm standard CMOS process MK Hati, TK Bhattacharyya 2011 International Conference on Communications and Signal Processing, 9-13, 2011 | 13 | 2011 |
A power efficient and constant-gm1.8 V CMOS operational transconductance amplifier with rail-to-rail input and output ranges for charge pump in phase-locked loop MK Hati, TK Bhattacharyya 2012 International Conference on Devices, Circuits and Systems (ICDCS), 38-43, 2012 | 12 | 2012 |
A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer MK Hati, TK Bhattacharyya Microelectronics Journal 52, 134-146, 2016 | 11 | 2016 |
Efficient design technique for pulse swallow based fractional-N frequency divider MK Hati, TK Bhattacharyya 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 457-460, 2015 | 11 | 2015 |
A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizer MK Hati, TK Bhattacharyya Microelectronics Journal 61, 21-34, 2017 | 8 | 2017 |
A novel pulse swallow based frequency divider circuit for a phase-locked loops MK Hati, TK Bhattacharyya Analog Integrated Circuits and Signal Processing 92 (1), 55-69, 2017 | 7 | 2017 |
Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops MK Hati, TK Bhattacharyya Integration 63, 115-129, 2018 | 6 | 2018 |
A 55-mW 300MS/s 8-bit CMOS parallel pipeline ADC MK Hati, TK Bhattacharyya 2012 25th International Conference on VLSI Design, 45-50, 2012 | 6 | 2012 |
A high speed, low jitter and fast acquisition CMOS phase frequency detector for charge pump PLL MK Hati, TK Bhattacharyya Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 6 | 2012 |
A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation MK Hati, TK Bhattacharyya Integration 65, 175-188, 2019 | 3 | 2019 |
Implementation of a digital ΔΣ modulator and programmable prescaler divider circuit for a fractional-N PLL MK Hati, TK Bhattacharyya 2016 international conference on microelectronics, computing and …, 2016 | 3 | 2016 |
Dgital video broadcast services to handheld devices and a simplified DVB-H receiver subsystem MK Hati, TK Bhattacharyya 2012 National Conference on Communications (NCC), 1-5, 2012 | 2 | 2012 |
Auto Calibrated Delta Sigma Fractional-N PLL Frequency Synthesizer and aWideband Pipeline ADC MK Hati IIT, Kharagpur, 2017 | 1 | 2017 |
An 8-b 250-Msample/s power optimized pipelined A/D converter in 0.18-µm CMOS MK Hati, TK Bhattacharyya 2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015 | 1 | 2015 |
Implementation of dynamic element matching DAC and its use for noise cancellation in ΔΣ fractional-N PLL MK Hati, TK Bhattacharyya 2014 International Conference on Circuits, Power and Computing Technologies …, 2014 | 1 | 2014 |
An 8-b 250-Msample, s Power Optimized Pipelined AID Converter in O. 18-J-Lm CMOS MK Hati, TK Bhattacharyya 2015 International Conference on VLSI Systems, 0 | 1 | |
AUTOCALIBRATED DELTA-SIGMA FRACTIONAL-N FREQUENCY SYNTHESIZERS WITH LOOP BANDWIDTH CALIBRATION AND PHASE NOISE CANCELLATION USING PFD/DAC UNIT CURRENT CELL MK Hati, TK Bhattacharyya IN Patent 514,664, 2024 | | 2024 |