| Design and Verification of 4 X 4 Wallace Tree Multiplier M Esa, K Achyut The International Journal of Analytical and Experimental Modal Analysis., 2019 | 3 | 2019 |
| Industry 4.0: A Road Map to Custom Register Transfer Level Design SK Panda, K Achyut, SK Kulkarni Advances in Industry 4.0: Concepts and Applications 5, 21, 2022 | 1 | 2022 |
| Synthesis and Time Analysis of FPGA-Based DIT-FFT Module for Efficient VLSI Signal Processing Applications KADCP Siba Kumar Panda Explainable Machine Learning Models and Architectures, 2023 | | 2023 |
| An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System—Understanding Complexity SK Panda, K Achyut, SK Kulkarni, AA Raut, A Nayak Artificial Intelligence Applications and Reconfigurable Architectures, 35-62, 2023 | | 2023 |
| An intelligent verification management approach for efficient VLSI computing system LN Konasagar Achyut, Swati K. Kulkarni, Akshata A. Raut, Siba Kumar Panda Intelligent Network Design Driven by Big Data Analytics, IoT, AI and Cloud …, 2022 | | 2022 |
| RTL Verification and FPGA Implementation of 4x4 Vedic Multiplier. CS Mohd. Esa, Konasagar Achyut Parishodh Journal. 9 (3), 772-778, 2020 | | 2020 |
Mohd EsaResearch Fellow,Defence R&D Laboratory
Mohd EsaResearch Fellow,Defence R&D Laboratory