| A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device HT Lue, TH Hsu, YH Hsiao, SP Hong, MT Wu, FH Hsu, NZ Lien, SY Wang, ... 2010 Symposium on VLSI Technology, 131-132, 2010 | 422 | 2010 |
| Modeling and optimization of monolithic polycrystalline silicon resistors NCC Lu, L Gerzberg, CY Lu, JD Meindl IEEE transactions on electron devices 28 (7), 818-830, 1981 | 383 | 1981 |
| Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits CY Lu, J Sung US Patent 5,943,581, 1999 | 275 | 1999 |
| Data retention behavior of a SONOS type two-bit storage flash memory cell WJ Tsai, NK Zous, CJ Liu, CC Liu, CH Chen, T Wang, S Pan, CY Lu, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 232 | 2001 |
| Semiconductor device manufacture including trench formation KH Lee, CY Lu US Patent 4,952,524, 1990 | 227 | 1990 |
| Laser programmable electrically readable phase-change memory method and device CY Lu, YC Chen US Patent 6,850,432, 2005 | 205 | 2005 |
| Future challenges of flash memory technologies CY Lu, KY Hsieh, R Liu Microelectronic engineering 86 (3), 283-286, 2009 | 197 | 2009 |
| Roughened polysilicon surface capacitor electrode plate for high denity dram CY Lu US Patent 5,110,752, 1992 | 186 | 1992 |
| High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme CC Wu, DW Lin, A Keshavarzi, CH Huang, CT Chan, CH Tseng, CL Chen, ... 2010 International Electron Devices Meeting, 27.1. 1-27.1. 4, 2010 | 184 | 2010 |
| BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability HT Lue, SY Wang, EK Lai, YH Shih, SC Lai, LW Yang, KC Chen, J Ku, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 179 | 2005 |
| An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device YC Chen, CF Chen, CT Chen, JY Yu, S Wu, SL Lung, R Liu, CY Lu IEEE International Electron Devices Meeting 2003, 37.4. 1-37.4. 4, 2003 | 166 | 2003 |
| Design for high density memory with relaxed metal pitch HC Kirsch, CY Lu US Patent 6,057,573, 2000 | 157 | 2000 |
| A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon films NCC Lu, L Gerzberg, CY Lu, JD Meindl IEEE Transactions on electron devices 30 (2), 137-149, 1983 | 146 | 1983 |
| Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor MH Chi, CY Lu US Patent 6,171,923, 2001 | 141 | 2001 |
| PHINES: a novel low power program/erase, small pitch, 2-bit per cell flash memory CC Yeh, WJ Tsai, MI Liu, TC Lu, SK Cho, CJ Lin, T Wang, S Pan, CY Lu Digest. International Electron Devices Meeting,, 931-934, 2002 | 137 | 2002 |
| Cause of data retention loss in a nitride-based localized trapping storage flash memory cell WJ Tsai, SH Gu, NK Zous, CC Yeh, CC Liu, CH Chen, T Wang, S Pan, ... 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th …, 2002 | 136 | 2002 |
| Method for manufacturing a multiple-bit-per-cell memory CC Yeh, HC Lai, WJ Tsai, TC Lu, CY Lu US Patent 8,501,591, 2013 | 134 | 2013 |
| IEEE Trans. Electron Devices NCC Lu, L Gerzberg, CY Lu, JD Meindl IEEE Trans. Electron Devices 28 (7), 818, 1981 | 128 | 1981 |
| Vertical DRAM cross point memory cell and fabrication method CY Lu US Patent 5,396,093, 1995 | 124 | 1995 |
| Unipolar Switching Behaviors of RTO RRAM WC Chien, YC Chen, EK Lai, YD Yao, P Lin, SF Horng, J Gong, TH Chou, ... IEEE electron device letters 31 (2), 126-128, 2010 | 122 | 2010 |
