| Implementation of Bi-Directional Blue-Fi Gateway in IoT Envoriment HS P.Gopi Krishna,K.Srinivasa R P.Hareesh,D.Ajay Kumar International Journal of Engineering & Technology 7 (Special issue 8), 97-102, 2018 | 6* | 2018 |
| Detection of Volatile Organic Compounds Using Micro-Electro-Mechanical-Systems Microcantilever: A Review MNKRKB P Hareesh*, P Shanmugaraja, P H S T Murthy Computer Integrated Manufacturing Systems 28 (11), 861-882, 2022 | 2* | 2022 |
| Design of Microcantilever Based Sensor for Detection of Volatile Organic Compounds P Hareesh, P Shanmugaraja, PHS Tejomurthy Telematique, 7344–7353-7344–7353, 2022 | 1 | 2022 |
| Implementation of Area and Energy Efficient MOBTA Using FPGA NSAR P. Hareesh, M.Ravi kumar, Navya, M. Greeshma Computer Integrated Manufacturing Systems 28 (11), 841-847, 2022 | | 2022 |
| Area and delay efficient design for parallel Prefix finite field multiplier SF Ch Jaya Prakesh, P.Hareesh International Journal of Management, Technology And Engineering 8 (X), 2983-2988, 2018 | | 2018 |
| Concede Threshold Analysis for logic gate Designs PG P.Hareesh,Ch Jaya Prakash International Journal of Management, Technology And Engineering 8 (X), 1861-1867, 2018 | | 2018 |
| Design of DPLL and Implementation of BIST to Evaluate its Characteristics SVA P.Hareesh International Journal of Advance Engineering and Research Development 4 (11 …, 2017 | | 2017 |
| Design and implementation of Brent Kung carry select adder using pass transistor logic techniques P. Hareesh, A.Suresh Babu INTERNATIONAL JOURNAL OF RESEARCH IN ELECTRONICS & COMMUNICATION ENGINEERING …, 2016 | | 2016 |
| Hardware Implementation of Digital Watermarking System for Real Time Captured Image Transmitting P. HAREESH,PATIPALLA VENKATESH International Journal of Innovative Technologies 4 (10), 1733,1734,1735,1736, 2016 | | 2016 |
| Low Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Using Power Gating Techniques SAK P.Hareesh International Journal & Magazine of Engineering, Technology, Management and …, 2015 | | 2015 |
| Latency Optimized Square and Cube Architecture using Vedic Sutras CHS P.HAREESH International Journal of Scientific Engineering and Technology Research 4 …, 2015 | | 2015 |
| A Digital CMOS Parallel Counter Architecture AC P.Hareesh International Journal of Electrical, Electronics and Computer Systems …, 2014 | | 2014 |
| Design Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme MG P.Hareesh International Journal of Electrical, Electronics and Computer Systems …, 2014 | | 2014 |
| Exploiting Rising and Charge-Sharing Voltage for Power Management in High Speed Domino Circuits GNM P.Hareesh, R.Trinadh, V.Krishnan International Journal of Electronics & Communication Technology 5 (Spl 3 …, 2014 | | 2014 |
| MTCMOS Full Subtractor With Low Power Consumption and Reduced Leakage Power GLP P.Hareesh,K.HariKrishna International Journal of Electronics & Communication Technology 5 (Spl-3 …, 2014 | | 2014 |
| STDFF A PASS TRANSISTOR BASED FLIP FLOP DESIGN FOR EFFICIENT INTEGRATED CIRCUITS P.HAREESH,G.LAKSHMI PRANEETHA International Journal of Electronics Signals and Systems (IJESS), ISSN: 2231 …, 2013 | | 2013 |
| A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING READ STABILITY WITH REDUCED TRANSISTOR COUNT FOR FUTURE CACHES KHK P.HAREESH International Journal of Electronics Signals and Systems (IJESS), ISSN: 2231 …, 2013 | | 2013 |
Dr. Gopi Krishna PopuriKoneru Lakshmaiah Education FoundationVerified email at kluniversity.in
