| Fault modeling and simulation for crosstalk in system-on-chip interconnects M Cuviello, S Dey, X Bai, Y Zhao 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 333 | 1999 |
| System, method and computer program product for handling small aggressors in signal integrity analysis IK Xiaoliang Bai US Patent 7,562,323, 2009 | 173 | 2009 |
| System, method and computer program product for handling small aggressors in signal integrity analysis X Bai, I Keller US Patent 7,562,323, 2009 | 173 | 2009 |
| Uncertainty-aware circuit optimization X Bai, C Visweswariah, PN Strenski Proceedings of the 39th annual Design Automation Conference, 58-63, 2002 | 134 | 2002 |
| Self-test methodology for at-speed test of crosstalk in chip interconnects X Bai, S Dey, J Rajski Proceedings of the 37th Annual Design Automation Conference, 619-624, 2000 | 118 | 2000 |
| A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits C Zhao, X Bai, S Dey Proceedings of the 41st annual Design Automation Conference, 894-899, 2004 | 113 | 2004 |
| Testing for interconnect crosstalk defects using on-chip embedded processor cores L Chen, X Bai, S Dey Proceedings of the 38th annual Design Automation Conference, 317-320, 2001 | 60 | 2001 |
| Parameter variation tolerant method for circuit design optimization DJ Hathaway, X Bai, C Visweswariah, PN Strenski US Patent 6,826,733, 2004 | 44 | 2004 |
| HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. X Bai, S Dey, A Krstic ITC 3, 112121, 2003 | 40 | 2003 |
| Evaluating transient error effects in digital nanometer circuits C Zhao, X Bai, S Dey IEEE Transactions on Reliability 56 (3), 381-391, 2007 | 39 | 2007 |
| High-level crosstalk defect simulation for system-on-chip interconnects X Bai, S Dey Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 169-175, 2001 | 35 | 2001 |
| Soft-spot analysis: targeting compound noise effects in nanometer circuits C Zhao, S Dey, X Bai IEEE Design & Test of Computers 22 (4), 362-375, 2005 | 32 | 2005 |
| Asynchronous control of memory self test RD Adams, R Abbott, X Bai, DM Burek US Patent 7,203,873, 2007 | 29 | 2007 |
| High-level crosstalk defect simulation methodology for system-on-chip interconnects X Bai, S Dey IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 23 | 2004 |
| Noise-aware driver modeling for nanometer technology X Bai, R Chandra, S Dey, PV Srinivas Fourth International Symposium on Quality Electronic Design, 2003 …, 2003 | 16 | 2003 |
| Method for test application and test content generation for AC faults in integrated circuits S Dey, X Bai, L Chen, A Krstic US Patent App. 10/951,278, 2005 | 14 | 2005 |
| Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits X Bai, R Chandra, S Dey, PV Srinivas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 14 | 2004 |
| A New Statisitcal Setup and Hold Time Definition X Bai, X Zhang, P Patel IC Design & Technology (ICICDT), 2012 IEEE International Conference on, 1-4, 2012 | 11 | 2012 |
| A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits C Zhao, X Bai, S Dey IEEE International Conference on Test, 2005., 10 pp.-1058, 2005 | 11 | 2005 |
| An integrated memory self test and EDA solution RD Adams, R Abbott, X Bai, D Burek, E MacDonald Records of the 2004 International Workshop on Memory Technology, Design and …, 2004 | 11 | 2004 |
