| Two-dimensional transistors with reconfigurable polarities for secure circuits P Wu, D Reis, XS Hu, J Appenzeller Nature Electronics 4 (1), 45-53, 2021 | 122 | 2021 |
| Understanding contact gating in Schottky barrier transistors from 2D channels A Prakash, H Ilatikhameneh, P Wu, J Appenzeller Scientific reports 7 (1), 12596, 2017 | 109 | 2017 |
| Complementary Black Phosphorus Tunneling Field-Effect Transistors P Wu, T Ameen, H Zhang, LA Bendersky, H Ilatikhameneh, G Klimeck, ... ACS nano 13 (1), 377-385, 2018 | 94 | 2018 |
| Characterization of Single Defects in Ultrascaled MoS2 Field-Effect Transistors B Stampfer, F Zhang, YY Illarionov, T Knobloch, P Wu, M Waltl, A Grill, ... ACS nano 12 (6), 5368-5375, 2018 | 60 | 2018 |
| Memory applications from 2D materials CC Chiang, V Ostwal, P Wu, CS Pang, F Zhang, Z Chen, J Appenzeller Applied Physics Reviews 8 (2), 021306, 2021 | 59 | 2021 |
| Reconfigurable Black Phosphorus Vertical Tunneling Field-Effect Transistor With Record High ON-Currents P Wu, J Appenzeller IEEE Electron Device Letters 40 (6), 981-984, 2019 | 34 | 2019 |
| Sub-1nm EOT WS2-FET with IDS > 600μA/μm at VDS=1V and SS < 70mV/dec at LG=40nm CS Pang, P Wu, J Appenzeller, Z Chen 2020 IEEE International Electron Devices Meeting (IEDM), 3.4. 1-3.4. 4, 2020 | 23 | 2020 |
| Mobility Extraction in 2D Transition Metal Dichalcogenide Devices—Avoiding Contact Resistance Implicated Overestimation CS Pang, R Zhou, X Liu, P Wu, TYT Hung, S Guo, ME Zaghloul, S Krylyuk, ... Small 17 (28), 2100940, 2021 | 22 | 2021 |
| Toward CMOS like devices from two-dimensional channel materials P Wu, J Appenzeller APL Materials 7 (10), 100701, 2019 | 17 | 2019 |
| Thickness-Dependent Study of High- Performance WS2-FETs With Ultrascaled Channel Lengths CS Pang, P Wu, J Appenzeller, Z Chen IEEE Transactions on Electron Devices 68 (4), 2123-2129, 2021 | 12 | 2021 |
| Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2 Z Sun, CS Pang, P Wu, TYT Hung, MY Li, SL Liew, CC Cheng, H Wang, ... ACS nano 16 (9), 14942-14950, 2022 | 11 | 2022 |
| Geometry Optimization of Planar Hall Devices Under Voltage Biasing G Zhang, J Zhang, Z Liu, P Wu, H Wu, H Qian, Y Wang, Z Zhang, Z Yu IEEE Transactions on Electron Devices 61 (12), 4216-4223, 2014 | 11 | 2014 |
| First demonstration of band-to-band tunneling in black phosphorus P Wu, A Prakash, J Appenzeller 2017 75th Annual Device Research Conference (DRC), 1-2, 2017 | 9 | 2017 |
| Artificial Sub-60 Millivolts/Decade Switching in a Metal–Insulator–Metal–Insulator–Semiconductor Transistor without a Ferroelectric Component P Wu, J Appenzeller ACS nano 15 (3), 5158-5164, 2021 | 8* | 2021 |
| Channel-potential based compact model of double-gate tunneling FETs considering channel-length scaling P Wu, J Zhang, L Zhang, Z Yu 2015 International Conference on Simulation of Semiconductor Processes and …, 2015 | 8 | 2015 |
| Vapour-phase deposition of two-dimensional layered chalcogenides T Zhang, J Wang, P Wu, AY Lu, J Kong Nature Reviews Materials 8 (12), 799-821, 2023 | 7 | 2023 |
| High Performance Complementary Black Phosphorus FETs and Inverter Circuits Operating at Record-Low V DD down to 0.2 V P Wu, J Appenzeller 2018 76th Device Research Conference (DRC), 1-2, 2018 | 7 | 2018 |
| Investigation of nitrogen enhanced NBTI effect using the universal prediction model P Wu, C Ma, L Zhang, X Lin, M Chan 2015 IEEE International Reliability Physics Symposium, XT. 5.1-XT. 5.4, 2015 | 7 | 2015 |
| Analysis of single electron traps in nano-scaled MoS2 FETs at cryogenic temperatures T Knobloch, J Michl, D Waldhör, Y Illarionov, B Stampfer, A Grill, R Zhou, ... Proceedings of the Device Research Conference (DRC), 52-53, 2020 | 6 | 2020 |
| Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part II: SRAM Circuit M Li, P Wu, B Zhou, J Appenzeller, XS Hu IEEE Transactions on Electron Devices 69 (11), 6085-6088, 2022 | 4 | 2022 |
Joerg AppenzellerProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
