| 13.1 A 940MHz-bandwidth 28.8 µs-period 8.9 GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications H Yeo, S Ryu, Y Lee, S Son, J Kim 2016 IEEE International Solid-State Circuits Conference (ISSCC), 238-239, 2016 | 46 | 2016 |
| A 9.2 GHz digital phase-locked loop with peaking-free transfer function S Ryu, H Yeo, Y Lee, S Son, J Kim IEEE Journal of Solid-State Circuits 49 (8), 1773-1784, 2014 | 28 | 2014 |
| A 2 Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery S Son, S Ryu, H Yeo, J Kim IEEE Journal of Solid-State Circuits 54 (10), 2823-2832, 2019 | 16 | 2019 |
| A 1.3-mW, 1.6-GHz digital delay-locked loop with two-cycle locking time and dither-free tracking K Kim, S Son, S Ryu, H Yeo, Y Choi, J Kim 2013 Symposium on VLSI Circuits, C158-C159, 2013 | 14 | 2013 |
| A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs J Kim, S Ryu, B Yoo, H Kim, Y Choi, DK Jeong 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 754-757, 2012 | 7 | 2012 |
| A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC S Ryu, CY Park, W Kim, S Son, J Kim IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2876-2889, 2021 | 4 | 2021 |
| An accurate and noise-resilient spread-spectrum clock tracking aid for digitally-controlled clock and data recovery loops S Ryu, S Son, J Kim IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 1245-1257, 2018 | 4 | 2018 |
| Synthesizing method of signal having variable frequency and synthesizer of signal having variable frequency JH Kim, HS Yeo, SG Ryu US Patent 9,385,732, 2016 | 4 | 2016 |
| A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems AS Assoa, A Bhat, S Ryu, A Raychowdhury Proceedings of the Great Lakes Symposium on VLSI 2023, 631-637, 2023 | 2 | 2023 |
| Cell-Based Construction of Mixed-Signal Systems Using Co-Design Flow of IC Compiler and Custom Designer: A Digital LL Example S Ryu, J Kim Proc. Synopsys SNUG, 2014 | 2 | 2014 |
| Fractionally-Spaced Equalizers as Clock and Data Recovery Loops S Ryu, J Kim, A Raychowdhury IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 | | 2024 |
| 30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256 pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance SD Spetalnick, AS Lele, B Crafton, M Chang, S Ryu, JH Yoon, Z Hao, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 482-484, 2024 | | 2024 |
| A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications S Ryu, AS Assoa, S Konno, A Raychowdhury 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | | 2023 |
| Design of Digital PLLs/CDRs with Novel Digital Circuit Techniques 류시강 서울대학교 대학원, 2019 | | 2019 |
